1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /* Copyright (c) 2012 Samsung Electronics Co. Ltd
4 * Exynos Phy register definitions
7 #ifndef _ASM_ARCH_XHCI_EXYNOS_H_
8 #define _ASM_ARCH_XHCI_EXYNOS_H_
10 /* Phy register MACRO definitions */
12 #define LINKSYSTEM_FLADJ_MASK (0x3f << 1)
13 #define LINKSYSTEM_FLADJ(_x) ((_x) << 1)
14 #define LINKSYSTEM_XHCI_VERSION_CONTROL (0x1 << 27)
16 #define PHYUTMI_OTGDISABLE (1 << 6)
17 #define PHYUTMI_FORCESUSPEND (1 << 1)
18 #define PHYUTMI_FORCESLEEP (1 << 0)
20 #define PHYCLKRST_SSC_REFCLKSEL_MASK (0xff << 23)
21 #define PHYCLKRST_SSC_REFCLKSEL(_x) ((_x) << 23)
23 #define PHYCLKRST_SSC_RANGE_MASK (0x03 << 21)
24 #define PHYCLKRST_SSC_RANGE(_x) ((_x) << 21)
26 #define PHYCLKRST_SSC_EN (0x1 << 20)
27 #define PHYCLKRST_REF_SSP_EN (0x1 << 19)
28 #define PHYCLKRST_REF_CLKDIV2 (0x1 << 18)
30 #define PHYCLKRST_MPLL_MULTIPLIER_MASK (0x7f << 11)
31 #define PHYCLKRST_MPLL_MULTIPLIER_100MHZ_REF (0x19 << 11)
32 #define PHYCLKRST_MPLL_MULTIPLIER_50M_REF (0x02 << 11)
33 #define PHYCLKRST_MPLL_MULTIPLIER_24MHZ_REF (0x68 << 11)
34 #define PHYCLKRST_MPLL_MULTIPLIER_20MHZ_REF (0x7d << 11)
35 #define PHYCLKRST_MPLL_MULTIPLIER_19200KHZ_REF (0x02 << 11)
37 #define PHYCLKRST_FSEL_MASK (0x3f << 5)
38 #define PHYCLKRST_FSEL(_x) ((_x) << 5)
39 #define PHYCLKRST_FSEL_PAD_100MHZ (0x27 << 5)
40 #define PHYCLKRST_FSEL_PAD_24MHZ (0x2a << 5)
41 #define PHYCLKRST_FSEL_PAD_20MHZ (0x31 << 5)
42 #define PHYCLKRST_FSEL_PAD_19_2MHZ (0x38 << 5)
44 #define PHYCLKRST_RETENABLEN (0x1 << 4)
46 #define PHYCLKRST_REFCLKSEL_MASK (0x03 << 2)
47 #define PHYCLKRST_REFCLKSEL_PAD_REFCLK (0x2 << 2)
48 #define PHYCLKRST_REFCLKSEL_EXT_REFCLK (0x3 << 2)
50 #define PHYCLKRST_PORTRESET (0x1 << 1)
51 #define PHYCLKRST_COMMONONN (0x1 << 0)
53 #define PHYPARAM0_REF_USE_PAD (0x1 << 31)
54 #define PHYPARAM0_REF_LOSLEVEL_MASK (0x1f << 26)
55 #define PHYPARAM0_REF_LOSLEVEL (0x9 << 26)
57 #define PHYPARAM1_PCS_TXDEEMPH_MASK (0x1f << 0)
58 #define PHYPARAM1_PCS_TXDEEMPH (0x1c)
60 #define PHYTEST_POWERDOWN_SSP (0x1 << 3)
61 #define PHYTEST_POWERDOWN_HSP (0x1 << 2)
63 #define PHYBATCHG_UTMI_CLKSEL (0x1 << 2)
65 #define FSEL_CLKSEL_24M (0x5)
67 /* XHCI PHY register structure */
68 struct exynos_usb3_phy {
69 unsigned int reserve1;
70 unsigned int link_system;
71 unsigned int phy_utmi;
72 unsigned int phy_pipe;
73 unsigned int phy_clk_rst;
74 unsigned int phy_reg0;
75 unsigned int phy_reg1;
76 unsigned int phy_param0;
77 unsigned int phy_param1;
78 unsigned int phy_term;
79 unsigned int phy_test;
81 unsigned int phy_batchg;
82 unsigned int phy_resume;
83 unsigned int reserve2[3];
84 unsigned int link_port;
87 #endif /* _ASM_ARCH_XHCI_EXYNOS_H_ */