1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * (C) Copyright 2012 Samsung Electronics
4 * Donghwa Lee <dh09.lee@samsung.com>
7 #ifndef __ASM_ARM_ARCH_SYSTEM_H_
8 #define __ASM_ARM_ARCH_SYSTEM_H_
11 struct exynos4_sysreg {
12 unsigned char res1[0x210];
13 unsigned int display_ctrl;
14 unsigned int display_ctrl2;
15 unsigned int camera_control;
16 unsigned int audio_endian;
17 unsigned int jtag_con;
20 struct exynos5_sysreg {
21 unsigned char res1[0x214];
22 unsigned int disp1blk_cfg;
23 unsigned int disp2blk_cfg;
24 unsigned int hdcp_e_fuse;
25 unsigned int gsclblk_cfg0;
26 unsigned int gsclblk_cfg1;
27 unsigned int reserved;
28 unsigned int ispblk_cfg;
29 unsigned int usb20phy_cfg;
30 unsigned char res2[0x29c];
31 unsigned int mipi_dphy;
32 unsigned int dptx_dphy;
33 unsigned int phyclk_sel;
37 #define USB20_PHY_CFG_HOST_LINK_EN (1 << 0)
40 * This instruction causes an event to be signaled to all cores
41 * within a multiprocessor system. If SEV is implemented,
42 * WFE must also be implemented.
44 #define sev() __asm__ __volatile__ ("sev\n\t" : : );
46 * If the Event Register is not set, WFE suspends execution until
47 * one of the following events occurs:
48 * - an IRQ interrupt, unless masked by the CPSR I-bit
49 * - an FIQ interrupt, unless masked by the CPSR F-bit
50 * - an Imprecise Data abort, unless masked by the CPSR A-bit
51 * - a Debug Entry request, if Debug is enabled
52 * - an Event signaled by another processor using the SEV instruction.
53 * If the Event Register is set, WFE clears it and returns immediately.
54 * If WFE is implemented, SEV must also be implemented.
56 #define wfe() __asm__ __volatile__ ("wfe\n\t" : : );
58 /* Move 0xd3 value to CPSR register to enable SVC mode */
59 #define svc32_mode_en() __asm__ __volatile__ \
60 ("@ I&F disable, Mode: 0x13 - SVC\n\t" \
61 "msr cpsr_c, #0x13|0xC0\n\t" : : )
63 /* Set program counter with the given value */
64 #define set_pc(x) __asm__ __volatile__ ("mov pc, %0\n\t" : : "r"(x))
66 /* Branch to the given location */
67 #define branch_bx(x) __asm__ __volatile__ ("bx %0\n\t" : : "r"(x))
69 /* Read Main Id register */
70 #define mrc_midr(x) __asm__ __volatile__ \
71 ("mrc p15, 0, %0, c0, c0, 0\n\t" : "=r"(x) : )
73 /* Read Multiprocessor Affinity Register */
74 #define mrc_mpafr(x) __asm__ __volatile__ \
75 ("mrc p15, 0, %0, c0, c0, 5\n\t" : "=r"(x) : )
77 /* Read System Control Register */
78 #define mrc_sctlr(x) __asm__ __volatile__ \
79 ("mrc p15, 0, %0, c1, c0, 0\n\t" : "=r"(x) : )
81 /* Read Auxiliary Control Register */
82 #define mrc_auxr(x) __asm__ __volatile__ \
83 ("mrc p15, 0, %0, c1, c0, 1\n\t" : "=r"(x) : )
85 /* Read L2 Control register */
86 #define mrc_l2_ctlr(x) __asm__ __volatile__ \
87 ("mrc p15, 1, %0, c9, c0, 2\n\t" : "=r"(x) : )
89 /* Read L2 Auxilliary Control register */
90 #define mrc_l2_aux_ctlr(x) __asm__ __volatile__ \
91 ("mrc p15, 1, %0, c15, c0, 0\n\t" : "=r"(x) : )
93 /* Write System Control Register */
94 #define mcr_sctlr(x) __asm__ __volatile__ \
95 ("mcr p15, 0, %0, c1, c0, 0\n\t" : : "r"(x))
97 /* Write Auxiliary Control Register */
98 #define mcr_auxr(x) __asm__ __volatile__ \
99 ("mcr p15, 0, %0, c1, c0, 1\n\t" : : "r"(x))
101 /* Invalidate all instruction caches to PoU */
102 #define mcr_icache(x) __asm__ __volatile__ \
103 ("mcr p15, 0, %0, c7, c5, 0\n\t" : : "r"(x))
105 /* Invalidate unified TLB */
106 #define mcr_tlb(x) __asm__ __volatile__ \
107 ("mcr p15, 0, %0, c8, c7, 0\n\t" : : "r"(x))
109 /* Write L2 Control register */
110 #define mcr_l2_ctlr(x) __asm__ __volatile__ \
111 ("mcr p15, 1, %0, c9, c0, 2\n\t" : : "r"(x))
113 /* Write L2 Auxilliary Control register */
114 #define mcr_l2_aux_ctlr(x) __asm__ __volatile__ \
115 ("mcr p15, 1, %0, c15, c0, 0\n\t" : : "r"(x))
117 void set_usbhost_mode(unsigned int mode);
118 void set_system_display_ctrl(void);
119 int exynos_lcd_early_init(const void *blob);
121 #endif /* _EXYNOS4_SYSTEM_H */