arch/arm/mach-exynos/include/mach/fb.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * (C) Copyright 2012 Samsung Electronics
   4  * Donghwa Lee <dh09.lee@samsung.com>
   5  */
   6
   7 #ifndef __ASM_ARM_ARCH_FB_H_
   8 #define __ASM_ARM_ARCH_FB_H_
   9
  10 #ifndef __ASSEMBLY__
  11 struct exynos_fb {
  12         unsigned int vidcon0;
  13         unsigned int vidcon1;
  14         unsigned int vidcon2;
  15         unsigned int vidcon3;
  16         unsigned int vidtcon0;
  17         unsigned int vidtcon1;
  18         unsigned int vidtcon2;
  19         unsigned int vidtcon3;
  20         unsigned int wincon0;
  21         unsigned int wincon1;
  22         unsigned int wincon2;
  23         unsigned int wincon3;
  24         unsigned int wincon4;
  25
  26         unsigned int winshmap;
  27         unsigned int res1;
  28
  29         unsigned int winchmap2;
  30         unsigned int vidosd0a;
  31         unsigned int vidosd0b;
  32         unsigned int vidosd0c;
  33         unsigned int res2;
  34
  35         unsigned int vidosd1a;
  36         unsigned int vidosd1b;
  37         unsigned int vidosd1c;
  38         unsigned int vidosd1d;
  39
  40         unsigned int vidosd2a;
  41         unsigned int vidosd2b;
  42         unsigned int vidosd2c;
  43         unsigned int vidosd2d;
  44
  45         unsigned int vidosd3a;
  46         unsigned int vidosd3b;
  47         unsigned int vidosd3c;
  48         unsigned int res3;
  49
  50         unsigned int vidosd4a;
  51         unsigned int vidosd4b;
  52         unsigned int vidosd4c;
  53         unsigned int res4[5];
  54
  55         unsigned int vidw00add0b0;
  56         unsigned int vidw00add0b1;
  57         unsigned int vidw01add0b0;
  58         unsigned int vidw01add0b1;
  59
  60         unsigned int vidw02add0b0;
  61         unsigned int vidw02add0b1;
  62         unsigned int vidw03add0b0;
  63         unsigned int vidw03add0b1;
  64         unsigned int vidw04add0b0;
  65         unsigned int vidw04add0b1;
  66         unsigned int res5[2];
  67
  68         unsigned int vidw00add1b0;
  69         unsigned int vidw00add1b1;
  70         unsigned int vidw01add1b0;
  71         unsigned int vidw01add1b1;
  72
  73         unsigned int vidw02add1b0;
  74         unsigned int vidw02add1b1;
  75         unsigned int vidw03add1b0;
  76         unsigned int vidw03add1b1;
  77
  78         unsigned int vidw04add1b0;
  79         unsigned int vidw04add1b1;
  80         unsigned int res7[2];
  81
  82         unsigned int vidw00add2;
  83         unsigned int vidw01add2;
  84         unsigned int vidw02add2;
  85         unsigned int vidw03add2;
  86         unsigned int vidw04add2;
  87         unsigned int res8[7];
  88
  89         unsigned int vidintcon0;
  90         unsigned int vidintcon1;
  91         unsigned int res9[1];
  92
  93         unsigned int w1keycon0;
  94         unsigned int w1keycon1;
  95         unsigned int w2keycon0;
  96         unsigned int w2keycon1;
  97         unsigned int w3keycon0;
  98         unsigned int w3keycon1;
  99         unsigned int w4keycon0;
 100         unsigned int w4keycon1;
 101
 102         unsigned int w1keyalpha;
 103         unsigned int w2keyalpha;
 104         unsigned int w3keyalpha;
 105         unsigned int w4keyalpha;
 106
 107         unsigned int dithmode;
 108         unsigned int res10[2];
 109
 110         unsigned int win0map;
 111         unsigned int win1map;
 112         unsigned int win2map;
 113         unsigned int win3map;
 114         unsigned int win4map;
 115         unsigned int res11[1];
 116
 117         unsigned int wpalcon_h;
 118         unsigned int wpalcon_l;
 119
 120         unsigned int trigcon;
 121         unsigned int res12[2];
 122
 123         unsigned int i80ifcona0;
 124         unsigned int i80ifcona1;
 125         unsigned int i80ifconb0;
 126         unsigned int i80ifconb1;
 127
 128         unsigned int colorgaincon;
 129         unsigned int res13[2];
 130
 131         unsigned int ldi_cmdcon0;
 132         unsigned int ldi_cmdcon1;
 133         unsigned int res14[1];
 134
 135         /* To be updated */
 136
 137         unsigned char res15[156];
 138         unsigned int dualrgb;
 139         unsigned char res16[16];
 140         unsigned int dp_mie_clkcon;
 141 };
 142 #endif
 143
 144 /* LCD IF register offset */
 145 #define EXYNOS4_LCD_IF_BASE_OFFSET                      0x0
 146 #define EXYNOS5_LCD_IF_BASE_OFFSET                      0x20000
 147
 148 static inline unsigned int exynos_fimd_get_base_offset(void)
 149 {
 150         if (cpu_is_exynos5())
 151                 return EXYNOS5_LCD_IF_BASE_OFFSET;
 152         else
 153                 return EXYNOS4_LCD_IF_BASE_OFFSET;
 154 }
 155
 156 /*
 157  *  Register offsets
 158 */
 159 #define EXYNOS_WINCON(x)                                (x * 0x04)
 160 #define EXYNOS_VIDOSD(x)                                (x * 0x10)
 161 #define EXYNOS_BUFFER_OFFSET(x)                         (x * 0x08)
 162 #define EXYNOS_BUFFER_SIZE(x)                           (x * 0x04)
 163
 164 /*
 165  * Bit Definitions
 166 */
 167
 168 /* VIDCON0 */
 169 #define EXYNOS_VIDCON0_DSI_DISABLE                      (0 << 30)
 170 #define EXYNOS_VIDCON0_DSI_ENABLE                       (1 << 30)
 171 #define EXYNOS_VIDCON0_SCAN_PROGRESSIVE                 (0 << 29)
 172 #define EXYNOS_VIDCON0_SCAN_INTERLACE                   (1 << 29)
 173 #define EXYNOS_VIDCON0_SCAN_MASK                        (1 << 29)
 174 #define EXYNOS_VIDCON0_VIDOUT_RGB                       (0 << 26)
 175 #define EXYNOS_VIDCON0_VIDOUT_ITU                       (1 << 26)
 176 #define EXYNOS_VIDCON0_VIDOUT_I80LDI0                   (2 << 26)
 177 #define EXYNOS_VIDCON0_VIDOUT_I80LDI1                   (3 << 26)
 178 #define EXYNOS_VIDCON0_VIDOUT_WB_RGB                    (4 << 26)
 179 #define EXYNOS_VIDCON0_VIDOUT_WB_I80LDI0                (6 << 26)
 180 #define EXYNOS_VIDCON0_VIDOUT_WB_I80LDI1                (7 << 26)
 181 #define EXYNOS_VIDCON0_VIDOUT_MASK                      (7 << 26)
 182 #define EXYNOS_VIDCON0_PNRMODE_RGB_P                    (0 << 17)
 183 #define EXYNOS_VIDCON0_PNRMODE_BGR_P                    (1 << 17)
 184 #define EXYNOS_VIDCON0_PNRMODE_RGB_S                    (2 << 17)
 185 #define EXYNOS_VIDCON0_PNRMODE_BGR_S                    (3 << 17)
 186 #define EXYNOS_VIDCON0_PNRMODE_MASK                     (3 << 17)
 187 #define EXYNOS_VIDCON0_PNRMODE_SHIFT                    (17)
 188 #define EXYNOS_VIDCON0_CLKVALUP_ALWAYS                  (0 << 16)
 189 #define EXYNOS_VIDCON0_CLKVALUP_START_FRAME             (1 << 16)
 190 #define EXYNOS_VIDCON0_CLKVALUP_MASK                    (1 << 16)
 191 #define EXYNOS_VIDCON0_CLKVAL_F(x)                      (((x) & 0xff) << 6)
 192 #define EXYNOS_VIDCON0_VCLKEN_NORMAL                    (0 << 5)
 193 #define EXYNOS_VIDCON0_VCLKEN_FREERUN                   (1 << 5)
 194 #define EXYNOS_VIDCON0_VCLKEN_MASK                      (1 << 5)
 195 #define EXYNOS_VIDCON0_CLKDIR_DIRECTED                  (0 << 4)
 196 #define EXYNOS_VIDCON0_CLKDIR_DIVIDED                   (1 << 4)
 197 #define EXYNOS_VIDCON0_CLKDIR_MASK                      (1 << 4)
 198 #define EXYNOS_VIDCON0_CLKSEL_HCLK                      (0 << 2)
 199 #define EXYNOS_VIDCON0_CLKSEL_SCLK                      (1 << 2)
 200 #define EXYNOS_VIDCON0_CLKSEL_MASK                      (1 << 2)
 201 #define EXYNOS_VIDCON0_ENVID_ENABLE                     (1 << 1)
 202 #define EXYNOS_VIDCON0_ENVID_DISABLE                    (0 << 1)
 203 #define EXYNOS_VIDCON0_ENVID_F_ENABLE                   (1 << 0)
 204 #define EXYNOS_VIDCON0_ENVID_F_DISABLE                  (0 << 0)
 205
 206 /* VIDCON1 */
 207 #define EXYNOS_VIDCON1_IVCLK_FALLING_EDGE               (0 << 7)
 208 #define EXYNOS_VIDCON1_IVCLK_RISING_EDGE                (1 << 7)
 209 #define EXYNOS_VIDCON1_IHSYNC_NORMAL                    (0 << 6)
 210 #define EXYNOS_VIDCON1_IHSYNC_INVERT                    (1 << 6)
 211 #define EXYNOS_VIDCON1_IVSYNC_NORMAL                    (0 << 5)
 212 #define EXYNOS_VIDCON1_IVSYNC_INVERT                    (1 << 5)
 213 #define EXYNOS_VIDCON1_IVDEN_NORMAL                     (0 << 4)
 214 #define EXYNOS_VIDCON1_IVDEN_INVERT                     (1 << 4)
 215
 216 /* VIDCON2 */
 217 #define EXYNOS_VIDCON2_EN601_DISABLE                    (0 << 23)
 218 #define EXYNOS_VIDCON2_EN601_ENABLE                     (1 << 23)
 219 #define EXYNOS_VIDCON2_EN601_MASK                       (1 << 23)
 220 #define EXYNOS_VIDCON2_WB_DISABLE                       (0 << 15)
 221 #define EXYNOS_VIDCON2_WB_ENABLE                        (1 << 15)
 222 #define EXYNOS_VIDCON2_WB_MASK                          (1 << 15)
 223 #define EXYNOS_VIDCON2_TVFORMATSEL_HW                   (0 << 14)
 224 #define EXYNOS_VIDCON2_TVFORMATSEL_SW                   (1 << 14)
 225 #define EXYNOS_VIDCON2_TVFORMATSEL_MASK                 (1 << 14)
 226 #define EXYNOS_VIDCON2_TVFORMATSEL_YUV422               (1 << 12)
 227 #define EXYNOS_VIDCON2_TVFORMATSEL_YUV444               (2 << 12)
 228 #define EXYNOS_VIDCON2_TVFORMATSEL_YUV_MASK             (3 << 12)
 229 #define EXYNOS_VIDCON2_ORGYUV_YCBCR                     (0 << 8)
 230 #define EXYNOS_VIDCON2_ORGYUV_CBCRY                     (1 << 8)
 231 #define EXYNOS_VIDCON2_ORGYUV_MASK                      (1 << 8)
 232 #define EXYNOS_VIDCON2_YUVORD_CBCR                      (0 << 7)
 233 #define EXYNOS_VIDCON2_YUVORD_CRCB                      (1 << 7)
 234 #define EXYNOS_VIDCON2_YUVORD_MASK                      (1 << 7)
 235
 236 /* PRTCON */
 237 #define EXYNOS_PRTCON_UPDATABLE                         (0 << 11)
 238 #define EXYNOS_PRTCON_PROTECT                           (1 << 11)
 239
 240 /* VIDTCON0 */
 241 #define EXYNOS_VIDTCON0_VBPDE(x)                        (((x) & 0xff) << 24)
 242 #define EXYNOS_VIDTCON0_VBPD(x)                         (((x) & 0xff) << 16)
 243 #define EXYNOS_VIDTCON0_VFPD(x)                         (((x) & 0xff) << 8)
 244 #define EXYNOS_VIDTCON0_VSPW(x)                         (((x) & 0xff) << 0)
 245
 246 /* VIDTCON1 */
 247 #define EXYNOS_VIDTCON1_VFPDE(x)                        (((x) & 0xff) << 24)
 248 #define EXYNOS_VIDTCON1_HBPD(x)                         (((x) & 0xff) << 16)
 249 #define EXYNOS_VIDTCON1_HFPD(x)                         (((x) & 0xff) << 8)
 250 #define EXYNOS_VIDTCON1_HSPW(x)                         (((x) & 0xff) << 0)
 251
 252 /* VIDTCON2 */
 253 #define EXYNOS_VIDTCON2_LINEVAL(x)                      (((x) & 0x7ff) << 11)
 254 #define EXYNOS_VIDTCON2_HOZVAL(x)                       (((x) & 0x7ff) << 0)
 255 #define EXYNOS_VIDTCON2_LINEVAL_E(x)                    ((((x) & 0x800) >> 11) << 23)
 256 #define EXYNOS_VIDTCON2_HOZVAL_E(x)                     ((((x) & 0x800) >> 11) << 22)
 257
 258 /* Window 0~4 Control - WINCONx */
 259 #define EXYNOS_WINCON_DATAPATH_DMA                      (0 << 22)
 260 #define EXYNOS_WINCON_DATAPATH_LOCAL                    (1 << 22)
 261 #define EXYNOS_WINCON_DATAPATH_MASK                     (1 << 22)
 262 #define EXYNOS_WINCON_BUFSEL_0                          (0 << 20)
 263 #define EXYNOS_WINCON_BUFSEL_1                          (1 << 20)
 264 #define EXYNOS_WINCON_BUFSEL_MASK                       (1 << 20)
 265 #define EXYNOS_WINCON_BUFSEL_SHIFT                      (20)
 266 #define EXYNOS_WINCON_BUFAUTO_DISABLE                   (0 << 19)
 267 #define EXYNOS_WINCON_BUFAUTO_ENABLE                    (1 << 19)
 268 #define EXYNOS_WINCON_BUFAUTO_MASK                      (1 << 19)
 269 #define EXYNOS_WINCON_BITSWP_DISABLE                    (0 << 18)
 270 #define EXYNOS_WINCON_BITSWP_ENABLE                     (1 << 18)
 271 #define EXYNOS_WINCON_BITSWP_SHIFT                      (18)
 272 #define EXYNOS_WINCON_BYTESWP_DISABLE                   (0 << 17)
 273 #define EXYNOS_WINCON_BYTESWP_ENABLE                    (1 << 17)
 274 #define EXYNOS_WINCON_BYTESWP_SHIFT                     (17)
 275 #define EXYNOS_WINCON_HAWSWP_DISABLE                    (0 << 16)
 276 #define EXYNOS_WINCON_HAWSWP_ENABLE                     (1 << 16)
 277 #define EXYNOS_WINCON_HAWSWP_SHIFT                      (16)
 278 #define EXYNOS_WINCON_WSWP_DISABLE                      (0 << 15)
 279 #define EXYNOS_WINCON_WSWP_ENABLE                       (1 << 15)
 280 #define EXYNOS_WINCON_WSWP_SHIFT                        (15)
 281 #define EXYNOS_WINCON_INRGB_RGB                         (0 << 13)
 282 #define EXYNOS_WINCON_INRGB_YUV                         (1 << 13)
 283 #define EXYNOS_WINCON_INRGB_MASK                        (1 << 13)
 284 #define EXYNOS_WINCON_BURSTLEN_16WORD                   (0 << 9)
 285 #define EXYNOS_WINCON_BURSTLEN_8WORD                    (1 << 9)
 286 #define EXYNOS_WINCON_BURSTLEN_4WORD                    (2 << 9)
 287 #define EXYNOS_WINCON_BURSTLEN_MASK                     (3 << 9)
 288 #define EXYNOS_WINCON_ALPHA_MULTI_DISABLE               (0 << 7)
 289 #define EXYNOS_WINCON_ALPHA_MULTI_ENABLE                (1 << 7)
 290 #define EXYNOS_WINCON_BLD_PLANE                         (0 << 6)
 291 #define EXYNOS_WINCON_BLD_PIXEL                         (1 << 6)
 292 #define EXYNOS_WINCON_BLD_MASK                          (1 << 6)
 293 #define EXYNOS_WINCON_BPPMODE_1BPP                      (0 << 2)
 294 #define EXYNOS_WINCON_BPPMODE_2BPP                      (1 << 2)
 295 #define EXYNOS_WINCON_BPPMODE_4BPP                      (2 << 2)
 296 #define EXYNOS_WINCON_BPPMODE_8BPP_PAL                  (3 << 2)
 297 #define EXYNOS_WINCON_BPPMODE_8BPP                      (4 << 2)
 298 #define EXYNOS_WINCON_BPPMODE_16BPP_565                 (5 << 2)
 299 #define EXYNOS_WINCON_BPPMODE_16BPP_A555                (6 << 2)
 300 #define EXYNOS_WINCON_BPPMODE_18BPP_666                 (8 << 2)
 301 #define EXYNOS_WINCON_BPPMODE_18BPP_A665                (9 << 2)
 302 #define EXYNOS_WINCON_BPPMODE_24BPP_888                 (0xb << 2)
 303 #define EXYNOS_WINCON_BPPMODE_24BPP_A887                (0xc << 2)
 304 #define EXYNOS_WINCON_BPPMODE_32BPP                     (0xd << 2)
 305 #define EXYNOS_WINCON_BPPMODE_16BPP_A444                (0xe << 2)
 306 #define EXYNOS_WINCON_BPPMODE_15BPP_555                 (0xf << 2)
 307 #define EXYNOS_WINCON_BPPMODE_MASK                      (0xf << 2)
 308 #define EXYNOS_WINCON_BPPMODE_SHIFT                     (2)
 309 #define EXYNOS_WINCON_ALPHA0_SEL                        (0 << 1)
 310 #define EXYNOS_WINCON_ALPHA1_SEL                        (1 << 1)
 311 #define EXYNOS_WINCON_ALPHA_SEL_MASK                    (1 << 1)
 312 #define EXYNOS_WINCON_ENWIN_DISABLE                     (0 << 0)
 313 #define EXYNOS_WINCON_ENWIN_ENABLE                      (1 << 0)
 314
 315 /* WINCON1 special */
 316 #define EXYNOS_WINCON1_VP_DISABLE                       (0 << 24)
 317 #define EXYNOS_WINCON1_VP_ENABLE                        (1 << 24)
 318 #define EXYNOS_WINCON1_LOCALSEL_FIMC1                   (0 << 23)
 319 #define EXYNOS_WINCON1_LOCALSEL_VP                      (1 << 23)
 320 #define EXYNOS_WINCON1_LOCALSEL_MASK                    (1 << 23)
 321
 322 /* WINSHMAP */
 323 #define EXYNOS_WINSHMAP_PROTECT(x)                      (((x) & 0x1f) << 10)
 324 #define EXYNOS_WINSHMAP_CH_ENABLE(x)                    (1 << (x))
 325 #define EXYNOS_WINSHMAP_CH_DISABLE(x)                   (1 << (x))
 326 #define EXYNOS_WINSHMAP_LOCAL_ENABLE(x)                 (0x20 << (x))
 327 #define EXYNOS_WINSHMAP_LOCAL_DISABLE(x)                (0x20 << (x))
 328
 329 /* VIDOSDxA, VIDOSDxB */
 330 #define EXYNOS_VIDOSD_LEFT_X(x)                         (((x) & 0x7ff) << 11)
 331 #define EXYNOS_VIDOSD_TOP_Y(x)                          (((x) & 0x7ff) << 0)
 332 #define EXYNOS_VIDOSD_RIGHT_X(x)                        (((x) & 0x7ff) << 11)
 333 #define EXYNOS_VIDOSD_BOTTOM_Y(x)                       (((x) & 0x7ff) << 0)
 334 #define EXYNOS_VIDOSD_RIGHT_X_E(x)                      (((x) & 0x1) << 23)
 335 #define EXYNOS_VIDOSD_BOTTOM_Y_E(x)                     (((x) & 0x1) << 22)
 336
 337 /* VIDOSD0C, VIDOSDxD */
 338 #define EXYNOS_VIDOSD_SIZE(x)                           (((x) & 0xffffff) << 0)
 339
 340 /* VIDOSDxC (1~4) */
 341 #define EXYNOS_VIDOSD_ALPHA0_R(x)                       (((x) & 0xf) << 20)
 342 #define EXYNOS_VIDOSD_ALPHA0_G(x)                       (((x) & 0xf) << 16)
 343 #define EXYNOS_VIDOSD_ALPHA0_B(x)                       (((x) & 0xf) << 12)
 344 #define EXYNOS_VIDOSD_ALPHA1_R(x)                       (((x) & 0xf) << 8)
 345 #define EXYNOS_VIDOSD_ALPHA1_G(x)                       (((x) & 0xf) << 4)
 346 #define EXYNOS_VIDOSD_ALPHA1_B(x)                       (((x) & 0xf) << 0)
 347 #define EXYNOS_VIDOSD_ALPHA0_SHIFT                      (12)
 348 #define EXYNOS_VIDOSD_ALPHA1_SHIFT                      (0)
 349
 350 /* Start Address */
 351 #define EXYNOS_VIDADDR_START_VBANK(x)                   (((x) & 0xff) << 24)
 352 #define EXYNOS_VIDADDR_START_VBASEU(x)                  (((x) & 0xffffff) << 0)
 353
 354 /* End Address */
 355 #define EXYNOS_VIDADDR_END_VBASEL(x)                    (((x) & 0xffffff) << 0)
 356
 357 /* Buffer Size */
 358 #define EXYNOS_VIDADDR_OFFSIZE(x)                       (((x) & 0x1fff) << 13)
 359 #define EXYNOS_VIDADDR_PAGEWIDTH(x)                     (((x) & 0x1fff) << 0)
 360 #define EXYNOS_VIDADDR_OFFSIZE_E(x)                     ((((x) & 0x2000) >> 13) << 27)
 361 #define EXYNOS_VIDADDR_PAGEWIDTH_E(x)                   ((((x) & 0x2000) >> 13) << 26)
 362
 363 /* WIN Color Map */
 364 #define EXYNOS_WINMAP_COLOR(x)                          ((x) & 0xffffff)
 365
 366 /* VIDINTCON0 */
 367 #define EXYNOS_VIDINTCON0_SYSMAINCON_DISABLE            (0 << 19)
 368 #define EXYNOS_VIDINTCON0_SYSMAINCON_ENABLE             (1 << 19)
 369 #define EXYNOS_VIDINTCON0_SYSSUBCON_DISABLE             (0 << 18)
 370 #define EXYNOS_VIDINTCON0_SYSSUBCON_ENABLE              (1 << 18)
 371 #define EXYNOS_VIDINTCON0_SYSIFDONE_DISABLE             (0 << 17)
 372 #define EXYNOS_VIDINTCON0_SYSIFDONE_ENABLE              (1 << 17)
 373 #define EXYNOS_VIDINTCON0_FRAMESEL0_BACK                (0 << 15)
 374 #define EXYNOS_VIDINTCON0_FRAMESEL0_VSYNC               (1 << 15)
 375 #define EXYNOS_VIDINTCON0_FRAMESEL0_ACTIVE              (2 << 15)
 376 #define EXYNOS_VIDINTCON0_FRAMESEL0_FRONT               (3 << 15)
 377 #define EXYNOS_VIDINTCON0_FRAMESEL0_MASK                (3 << 15)
 378 #define EXYNOS_VIDINTCON0_FRAMESEL1_NONE                (0 << 13)
 379 #define EXYNOS_VIDINTCON0_FRAMESEL1_BACK                (1 << 13)
 380 #define EXYNOS_VIDINTCON0_FRAMESEL1_VSYNC               (2 << 13)
 381 #define EXYNOS_VIDINTCON0_FRAMESEL1_FRONT               (3 << 13)
 382 #define EXYNOS_VIDINTCON0_INTFRMEN_DISABLE              (0 << 12)
 383 #define EXYNOS_VIDINTCON0_INTFRMEN_ENABLE               (1 << 12)
 384 #define EXYNOS_VIDINTCON0_FIFOSEL_WIN4                  (1 << 11)
 385 #define EXYNOS_VIDINTCON0_FIFOSEL_WIN3                  (1 << 10)
 386 #define EXYNOS_VIDINTCON0_FIFOSEL_WIN2                  (1 << 9)
 387 #define EXYNOS_VIDINTCON0_FIFOSEL_WIN1                  (1 << 6)
 388 #define EXYNOS_VIDINTCON0_FIFOSEL_WIN0                  (1 << 5)
 389 #define EXYNOS_VIDINTCON0_FIFOSEL_ALL                   (0x73 << 5)
 390 #define EXYNOS_VIDINTCON0_FIFOSEL_MASK                  (0x73 << 5)
 391 #define EXYNOS_VIDINTCON0_FIFOLEVEL_25                  (0 << 2)
 392 #define EXYNOS_VIDINTCON0_FIFOLEVEL_50                  (1 << 2)
 393 #define EXYNOS_VIDINTCON0_FIFOLEVEL_75                  (2 << 2)
 394 #define EXYNOS_VIDINTCON0_FIFOLEVEL_EMPTY               (3 << 2)
 395 #define EXYNOS_VIDINTCON0_FIFOLEVEL_FULL                (4 << 2)
 396 #define EXYNOS_VIDINTCON0_FIFOLEVEL_MASK                (7 << 2)
 397 #define EXYNOS_VIDINTCON0_INTFIFO_DISABLE               (0 << 1)
 398 #define EXYNOS_VIDINTCON0_INTFIFO_ENABLE                (1 << 1)
 399 #define EXYNOS_VIDINTCON0_INT_DISABLE                   (0 << 0)
 400 #define EXYNOS_VIDINTCON0_INT_ENABLE                    (1 << 0)
 401 #define EXYNOS_VIDINTCON0_INT_MASK                      (1 << 0)
 402
 403 /* VIDINTCON1 */
 404 #define EXYNOS_VIDINTCON1_INTVPPEND                     (1 << 5)
 405 #define EXYNOS_VIDINTCON1_INTI80PEND                    (1 << 2)
 406 #define EXYNOS_VIDINTCON1_INTFRMPEND                    (1 << 1)
 407 #define EXYNOS_VIDINTCON1_INTFIFOPEND                   (1 << 0)
 408
 409 /* WINMAP */
 410 #define EXYNOS_WINMAP_ENABLE                            (1 << 24)
 411
 412 /* WxKEYCON0 (1~4) */
 413 #define EXYNOS_KEYCON0_KEYBLEN_DISABLE                  (0 << 26)
 414 #define EXYNOS_KEYCON0_KEYBLEN_ENABLE                   (1 << 26)
 415 #define EXYNOS_KEYCON0_KEY_DISABLE                      (0 << 25)
 416 #define EXYNOS_KEYCON0_KEY_ENABLE                       (1 << 25)
 417 #define EXYNOS_KEYCON0_DIRCON_MATCH_FG                  (0 << 24)
 418 #define EXYNOS_KEYCON0_DIRCON_MATCH_BG                  (1 << 24)
 419 #define EXYNOS_KEYCON0_COMPKEY(x)                       (((x) & 0xffffff) << 0)
 420
 421 /* WxKEYCON1 (1~4) */
 422 #define EXYNOS_KEYCON1_COLVAL(x)                        (((x) & 0xffffff) << 0)
 423
 424 /* DUALRGB */
 425 #define EXYNOS_DUALRGB_BYPASS_SINGLE                    (0x00 << 0)
 426 #define EXYNOS_DUALRGB_BYPASS_DUAL                      (0x01 << 0)
 427 #define EXYNOS_DUALRGB_MIE_DUAL                         (0x10 << 0)
 428 #define EXYNOS_DUALRGB_MIE_SINGLE                       (0x11 << 0)
 429 #define EXYNOS_DUALRGB_LINESPLIT                        (0x0 << 2)
 430 #define EXYNOS_DUALRGB_FRAMESPLIT                       (0x1 << 2)
 431 #define EXYNOS_DUALRGB_SUB_CNT(x)                       ((x & 0xfff) << 4)
 432 #define EXYNOS_DUALRGB_VDEN_EN_DISABLE                  (0x0 << 16)
 433 #define EXYNOS_DUALRGB_VDEN_EN_ENABLE                   (0x1 << 16)
 434 #define EXYNOS_DUALRGB_MAIN_CNT(x)                      ((x & 0xfff) << 18)
 435
 436 /* I80IFCONA0 and I80IFCONA1 */
 437 #define EXYNOS_LCD_CS_SETUP(x)                          (((x) & 0xf) << 16)
 438 #define EXYNOS_LCD_WR_SETUP(x)                          (((x) & 0xf) << 12)
 439 #define EXYNOS_LCD_WR_ACT(x)                            (((x) & 0xf) << 8)
 440 #define EXYNOS_LCD_WR_HOLD(x)                           (((x) & 0xf) << 4)
 441 #define EXYNOS_RSPOL_LOW                                (0 << 2)
 442 #define EXYNOS_RSPOL_HIGH                               (1 << 2)
 443 #define EXYNOS_I80IFEN_DISABLE                          (0 << 0)
 444 #define EXYNOS_I80IFEN_ENABLE                           (1 << 0)
 445
 446 /* TRIGCON */
 447 #define EXYNOS_I80SOFT_TRIG_EN                          (1 << 0)
 448 #define EXYNOS_I80START_TRIG                            (1 << 1)
 449 #define EXYNOS_I80STATUS_TRIG_DONE                      (1 << 2)
 450
 451 /* DP_MIE_CLKCON */
 452 #define EXYNOS_DP_MIE_DISABLE                           (0 << 0)
 453 #define EXYNOS_DP_CLK_ENABLE                            (1 << 1)
 454 #define EXYNOS_MIE_CLK_ENABLE                           (3 << 0)
 455
 456 #endif /* _REGS_FB_H */