arch/arm/mach-exynos/include/mach/dp_info.h

   1 /*
   2  * Copyright (C) 2012 Samsung Electronics
   3  *
   4  * Author: Donghwa Lee <dh09.lee@samsung.com>
   5  *
   6  * SPDX-License-Identifier:     GPL-2.0+
   7  */
   8
   9 #ifndef _DP_INFO_H
  10 #define _DP_INFO_H
  11
  12 #define msleep(a)                       udelay(a * 1000)
  13
  14 #define DP_TIMEOUT_LOOP_COUNT           100
  15 #define MAX_CR_LOOP                     5
  16 #define MAX_EQ_LOOP                     4
  17
  18 #define EXYNOS_DP_SUCCESS               0
  19
  20 enum {
  21         DP_DISABLE,
  22         DP_ENABLE,
  23 };
  24
  25 struct edp_disp_info {
  26         char *name;
  27         unsigned int h_total;
  28         unsigned int h_res;
  29         unsigned int h_sync_width;
  30         unsigned int h_back_porch;
  31         unsigned int h_front_porch;
  32         unsigned int v_total;
  33         unsigned int v_res;
  34         unsigned int v_sync_width;
  35         unsigned int v_back_porch;
  36         unsigned int v_front_porch;
  37
  38         unsigned int v_sync_rate;
  39 };
  40
  41 struct edp_link_train_info {
  42         unsigned int lt_status;
  43
  44         unsigned int ep_loop;
  45         unsigned int cr_loop[4];
  46
  47 };
  48
  49 struct edp_video_info {
  50         unsigned int master_mode;
  51         unsigned int bist_mode;
  52         unsigned int bist_pattern;
  53
  54         unsigned int h_sync_polarity;
  55         unsigned int v_sync_polarity;
  56         unsigned int interlaced;
  57
  58         unsigned int color_space;
  59         unsigned int dynamic_range;
  60         unsigned int ycbcr_coeff;
  61         unsigned int color_depth;
  62 };
  63
  64 struct exynos_dp_priv {
  65         struct edp_disp_info disp_info;
  66         struct edp_link_train_info lt_info;
  67         struct edp_video_info video_info;
  68
  69         /*below info get from panel during training*/
  70         unsigned char lane_bw;
  71         unsigned char lane_cnt;
  72         unsigned char dpcd_rev;
  73         /*support enhanced frame cap */
  74         unsigned char dpcd_efc;
  75         struct exynos_dp *regs;
  76 };
  77
  78 enum analog_power_block {
  79         AUX_BLOCK,
  80         CH0_BLOCK,
  81         CH1_BLOCK,
  82         CH2_BLOCK,
  83         CH3_BLOCK,
  84         ANALOG_TOTAL,
  85         POWER_ALL
  86 };
  87
  88 enum pll_status {
  89         PLL_UNLOCKED = 0,
  90         PLL_LOCKED
  91 };
  92
  93 enum {
  94         COLOR_RGB,
  95         COLOR_YCBCR422,
  96         COLOR_YCBCR444
  97 };
  98
  99 enum {
 100         VESA,
 101         CEA
 102 };
 103
 104 enum {
 105         COLOR_YCBCR601,
 106         COLOR_YCBCR709
 107 };
 108
 109 enum {
 110         COLOR_6,
 111         COLOR_8,
 112         COLOR_10,
 113         COLOR_12
 114 };
 115
 116 enum {
 117         DP_LANE_BW_1_62 = 0x06,
 118         DP_LANE_BW_2_70 = 0x0a,
 119 };
 120
 121 enum {
 122         DP_LANE_CNT_1 = 1,
 123         DP_LANE_CNT_2 = 2,
 124         DP_LANE_CNT_4 = 4,
 125 };
 126
 127 enum {
 128         DP_DPCD_REV_10 = 0x10,
 129         DP_DPCD_REV_11 = 0x11,
 130 };
 131
 132 enum {
 133         DP_LT_NONE,
 134         DP_LT_START,
 135         DP_LT_CR,
 136         DP_LT_ET,
 137         DP_LT_FINISHED,
 138         DP_LT_FAIL,
 139 };
 140
 141 enum  {
 142         PRE_EMPHASIS_LEVEL_0,
 143         PRE_EMPHASIS_LEVEL_1,
 144         PRE_EMPHASIS_LEVEL_2,
 145         PRE_EMPHASIS_LEVEL_3,
 146 };
 147
 148 enum {
 149         PRBS7,
 150         D10_2,
 151         TRAINING_PTN1,
 152         TRAINING_PTN2,
 153         DP_NONE
 154 };
 155
 156 enum {
 157         VOLTAGE_LEVEL_0,
 158         VOLTAGE_LEVEL_1,
 159         VOLTAGE_LEVEL_2,
 160         VOLTAGE_LEVEL_3,
 161 };
 162
 163 enum pattern_type {
 164         NO_PATTERN,
 165         COLOR_RAMP,
 166         BALCK_WHITE_V_LINES,
 167         COLOR_SQUARE,
 168         INVALID_PATTERN,
 169         COLORBAR_32,
 170         COLORBAR_64,
 171         WHITE_GRAY_BALCKBAR_32,
 172         WHITE_GRAY_BALCKBAR_64,
 173         MOBILE_WHITEBAR_32,
 174         MOBILE_WHITEBAR_64
 175 };
 176
 177 enum {
 178         CALCULATED_M,
 179         REGISTER_M
 180 };
 181
 182 enum {
 183         VIDEO_TIMING_FROM_CAPTURE,
 184         VIDEO_TIMING_FROM_REGISTER
 185 };
 186
 187
 188 struct exynos_dp_platform_data {
 189         struct exynos_dp_priv *edp_dev_info;
 190 };
 191
 192 #ifdef CONFIG_EXYNOS_DP
 193 unsigned int exynos_init_dp(void);
 194 #else
 195 unsigned int exynos_init_dp(void)
 196 {
 197         return 0;
 198 }
 199 #endif
 200
 201 #endif /* _DP_INFO_H */