1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Machine Specific Values for SMDK5250 board based on EXYNOS5
5 * Copyright (C) 2012 Samsung Electronics
8 #ifndef _SMDK5250_SETUP_H
9 #define _SMDK5250_SETUP_H
12 #include <asm/arch/dmc.h>
14 #define NOT_AVAILABLE 0
15 #define DATA_MASK 0xFFFFF
17 #define ENABLE_BIT 0x1
18 #define DISABLE_BIT 0x0
19 #define CA_SWAP_EN (1 << 0)
22 #define set_pll(mdiv, pdiv, sdiv) (1<<31 | mdiv<<16 | pdiv<<8 | sdiv)
24 /* MEMCONTROL register bit fields */
25 #define DMC_MEMCONTROL_CLK_STOP_DISABLE (0 << 0)
26 #define DMC_MEMCONTROL_DPWRDN_DISABLE (0 << 1)
27 #define DMC_MEMCONTROL_DPWRDN_ACTIVE_PRECHARGE (0 << 2)
28 #define DMC_MEMCONTROL_TP_DISABLE (0 << 4)
29 #define DMC_MEMCONTROL_DSREF_DISABLE (0 << 5)
30 #define DMC_MEMCONTROL_DSREF_ENABLE (1 << 5)
31 #define DMC_MEMCONTROL_ADD_LAT_PALL_CYCLE(x) (x << 6)
33 #define DMC_MEMCONTROL_MEM_TYPE_LPDDR3 (7 << 8)
34 #define DMC_MEMCONTROL_MEM_TYPE_DDR3 (6 << 8)
35 #define DMC_MEMCONTROL_MEM_TYPE_LPDDR2 (5 << 8)
37 #define DMC_MEMCONTROL_MEM_WIDTH_32BIT (2 << 12)
39 #define DMC_MEMCONTROL_NUM_CHIP_1 (0 << 16)
40 #define DMC_MEMCONTROL_NUM_CHIP_2 (1 << 16)
42 #define DMC_MEMCONTROL_BL_8 (3 << 20)
43 #define DMC_MEMCONTROL_BL_4 (2 << 20)
45 #define DMC_MEMCONTROL_PZQ_DISABLE (0 << 24)
47 #define DMC_MEMCONTROL_MRR_BYTE_7_0 (0 << 25)
48 #define DMC_MEMCONTROL_MRR_BYTE_15_8 (1 << 25)
49 #define DMC_MEMCONTROL_MRR_BYTE_23_16 (2 << 25)
50 #define DMC_MEMCONTROL_MRR_BYTE_31_24 (3 << 25)
52 /* MEMCONFIG0 register bit fields */
53 #define DMC_MEMCONFIGX_CHIP_MAP_INTERLEAVED (1 << 12)
54 #define DMC_MEMCONFIG_CHIP_MAP_SPLIT (2 << 12)
55 #define DMC_MEMCONFIGX_CHIP_COL_10 (3 << 8)
56 #define DMC_MEMCONFIGX_CHIP_ROW_14 (2 << 4)
57 #define DMC_MEMCONFIGX_CHIP_ROW_15 (3 << 4)
58 #define DMC_MEMCONFIGX_CHIP_BANK_8 (3 << 0)
60 #define DMC_MEMBASECONFIGX_CHIP_BASE(x) (x << 16)
61 #define DMC_MEMBASECONFIGX_CHIP_MASK(x) (x << 0)
62 #define DMC_MEMBASECONFIG_VAL(x) ( \
63 DMC_MEMBASECONFIGX_CHIP_BASE(x) | \
64 DMC_MEMBASECONFIGX_CHIP_MASK(0x780) \
68 * As we use channel interleaving, therefore value of the base address
69 * register must be set as half of the bus base address
70 * RAM start addess is 0x2000_0000 which means chip_base is 0x20, so
71 * we need to set half 0x10 to the membaseconfigx registers
72 * see exynos5420 UM section 17.17.3.21 for more.
74 #define DMC_CHIP_BASE_0 0x10
75 #define DMC_CHIP_BASE_1 0x50
76 #define DMC_CHIP_MASK 0x7C0
78 #define DMC_MEMBASECONFIG0_VAL DMC_MEMBASECONFIG_VAL(0x40)
79 #define DMC_MEMBASECONFIG1_VAL DMC_MEMBASECONFIG_VAL(0x80)
81 #define DMC_PRECHCONFIG_VAL 0xFF000000
82 #define DMC_PWRDNCONFIG_VAL 0xFFFF00FF
84 #define DMC_CONCONTROL_RESET_VAL 0x0FFF0000
85 #define DFI_INIT_START (1 << 28)
86 #define EMPTY (1 << 8)
87 #define AREF_EN (1 << 5)
89 #define DFI_INIT_COMPLETE_CHO (1 << 2)
90 #define DFI_INIT_COMPLETE_CH1 (1 << 3)
92 #define RDLVL_COMPLETE_CHO (1 << 14)
93 #define RDLVL_COMPLETE_CH1 (1 << 15)
95 #define CLK_STOP_EN (1 << 0)
96 #define DPWRDN_EN (1 << 1)
97 #define DSREF_EN (1 << 5)
99 /* COJCONTROL register bit fields */
100 #define DMC_CONCONTROL_IO_PD_CON_DISABLE (0 << 3)
101 #define DMC_CONCONTROL_IO_PD_CON_ENABLE (1 << 3)
102 #define DMC_CONCONTROL_AREF_EN_DISABLE (0 << 5)
103 #define DMC_CONCONTROL_AREF_EN_ENABLE (1 << 5)
104 #define DMC_CONCONTROL_EMPTY_DISABLE (0 << 8)
105 #define DMC_CONCONTROL_EMPTY_ENABLE (1 << 8)
106 #define DMC_CONCONTROL_RD_FETCH_DISABLE (0x0 << 12)
107 #define DMC_CONCONTROL_TIMEOUT_LEVEL0 (0xFFF << 16)
108 #define DMC_CONCONTROL_DFI_INIT_START_DISABLE (0 << 28)
110 #define DMC_CONCONTROL_VAL 0x1FFF2101
112 #define DREX_CONCONTROL_VAL DMC_CONCONTROL_VAL \
113 | DMC_CONCONTROL_AREF_EN_ENABLE \
114 | DMC_CONCONTROL_IO_PD_CON_ENABLE
116 #define DMC_CONCONTROL_IO_PD_CON(x) (x << 6)
119 #define HPM_RATIO 0x2
120 #define COPY_RATIO 0x0
122 /* CLK_DIV_CPU1 = 0x00000003 */
123 #define CLK_DIV_CPU1_VAL ((HPM_RATIO << 4) \
127 #define CLK_SRC_CORE0_VAL 0x00000000
130 #define CLK_SRC_CORE1_VAL 0x100
133 #define CLK_DIV_CORE0_VAL 0x00120000
136 #define CLK_DIV_CORE1_VAL 0x07070700
139 #define CLK_DIV_SYSRGT_VAL 0x00000111
142 #define CLK_DIV_ACP_VAL 0x12
145 #define CLK_DIV_SYSLFT_VAL 0x00000311
147 #define MUX_APLL_SEL_MASK (1 << 0)
148 #define MUX_MPLL_SEL_MASK (1 << 8)
149 #define MPLL_SEL_MOUT_MPLLFOUT (2 << 8)
150 #define MUX_CPLL_SEL_MASK (1 << 8)
151 #define MUX_EPLL_SEL_MASK (1 << 12)
152 #define MUX_VPLL_SEL_MASK (1 << 16)
153 #define MUX_GPLL_SEL_MASK (1 << 28)
154 #define MUX_BPLL_SEL_MASK (1 << 0)
155 #define MUX_HPM_SEL_MASK (1 << 20)
156 #define HPM_SEL_SCLK_MPLL (1 << 21)
157 #define PLL_LOCKED (1 << 29)
158 #define APLL_CON0_LOCKED (1 << 29)
159 #define MPLL_CON0_LOCKED (1 << 29)
160 #define BPLL_CON0_LOCKED (1 << 29)
161 #define CPLL_CON0_LOCKED (1 << 29)
162 #define EPLL_CON0_LOCKED (1 << 29)
163 #define GPLL_CON0_LOCKED (1 << 29)
164 #define VPLL_CON0_LOCKED (1 << 29)
165 #define CLK_REG_DISABLE 0x0
166 #define TOP2_VAL 0x0110000
168 /* SCLK_SRC_ISP - set SPI0/1 to 6 = SCLK_MPLL_USER */
169 #define SPI0_ISP_SEL 6
170 #define SPI1_ISP_SEL 6
171 #define SCLK_SRC_ISP_VAL (SPI1_ISP_SEL << 4) \
172 | (SPI0_ISP_SEL << 0)
174 /* SCLK_DIV_ISP - set SPI0/1 to 0xf = divide by 16 */
175 #define SPI0_ISP_RATIO 0xf
176 #define SPI1_ISP_RATIO 0xf
177 #define SCLK_DIV_ISP_VAL (SPI1_ISP_RATIO << 12) \
178 | (SPI0_ISP_RATIO << 0)
181 #define MMC2_RATIO_MASK 0xf
182 #define MMC2_RATIO_VAL 0x3
183 #define MMC2_RATIO_OFFSET 0
185 #define MMC2_PRE_RATIO_MASK 0xff
186 #define MMC2_PRE_RATIO_VAL 0x9
187 #define MMC2_PRE_RATIO_OFFSET 8
189 #define MMC3_RATIO_MASK 0xf
190 #define MMC3_RATIO_VAL 0x1
191 #define MMC3_RATIO_OFFSET 16
193 #define MMC3_PRE_RATIO_MASK 0xff
194 #define MMC3_PRE_RATIO_VAL 0x0
195 #define MMC3_PRE_RATIO_OFFSET 24
198 #define CLK_SRC_LEX_VAL 0x0
201 #define CLK_DIV_LEX_VAL 0x10
204 #define CLK_DIV_R0X_VAL 0x10
207 #define CLK_DIV_R1X_VAL 0x10
210 #define CLK_DIV_ISP2_VAL 0x1
213 #define SRC_KFC_HPM_SEL (1 << 15)
216 #define CLK_SRC_KFC_VAL 0x00008001
219 #define CLK_DIV_KFC_VAL 0x03300110
222 #define CLK_DIV2_RATIO 0x10111150
225 #define CLK_DIV4_RATIO 0x00000003
228 #define CLK_DIV_G2D 0x00000010
232 * For DP, divisor should be 2
234 #define CLK_DIV_DISP1_0_FIMD1 (2 << 0)
236 /* CLK_GATE_IP_DISP1 */
237 #define CLK_GATE_DP1_ALLOW (1 << 4)
240 #define AUDIO0_SEL_EPLL (0x6 << 28)
241 #define AUDIO0_RATIO 0x5
242 #define PCM0_RATIO 0x3
243 #define DIV_MAU_VAL (PCM0_RATIO << 24 | AUDIO0_RATIO << 20)
246 #define MUX_MCLK_CDR_MSPLL (1 << 4)
247 #define MUX_BPLL_SEL_FOUTBPLL (1 << 0)
248 #define BPLL_SEL_MASK 0x7
251 #define DDR3PHY_CTRL_PHY_RESET (1 << 0)
252 #define DDR3PHY_CTRL_PHY_RESET_OFF (0 << 0)
254 #define PHY_CON0_RESET_VAL 0x17020a40
255 #define P0_CMD_EN (1 << 14)
256 #define BYTE_RDLVL_EN (1 << 13)
257 #define CTRL_SHGATE (1 << 8)
259 #define PHY_CON1_RESET_VAL 0x09210100
260 #define RDLVL_PASS_ADJ_VAL 0x6
261 #define RDLVL_PASS_ADJ_OFFSET 16
262 #define CTRL_GATEDURADJ_MASK (0xf << 20)
263 #define READ_LEVELLING_DDR3 0x0100
265 #define PHY_CON2_RESET_VAL 0x00010004
266 #define INIT_DESKEW_EN (1 << 6)
267 #define DLL_DESKEW_EN (1 << 12)
268 #define RDLVL_GATE_EN (1 << 24)
269 #define RDLVL_EN (1 << 25)
270 #define RDLVL_INCR_ADJ (0x1 << 16)
273 #define DREX_PAUSE_EN (1 << 0)
275 #define BYPASS_EN (1 << 22)
278 #define PHY_CON0_VAL 0x17021A00
280 #define PHY_CON12_RESET_VAL 0x10100070
281 #define PHY_CON12_VAL 0x10107F50
282 #define CTRL_START (1 << 6)
283 #define CTRL_DLL_ON (1 << 5)
284 #define CTRL_LOCK_COARSE_OFFSET 10
285 #define CTRL_LOCK_COARSE_MASK (0x7F << CTRL_LOCK_COARSE_OFFSET)
286 #define CTRL_LOCK_COARSE(x) (((x) & CTRL_LOCK_COARSE_MASK) >> \
287 CTRL_LOCK_COARSE_OFFSET)
288 #define CTRL_FORCE_MASK (0x7F << 8)
289 #define CTRL_FINE_LOCKED 0x7
291 #define CTRL_OFFSETD_RESET_VAL 0x8
292 #define CTRL_OFFSETD_VAL 0x7F
294 #define CTRL_OFFSETR0 0x7F
295 #define CTRL_OFFSETR1 0x7F
296 #define CTRL_OFFSETR2 0x7F
297 #define CTRL_OFFSETR3 0x7F
298 #define PHY_CON4_VAL (CTRL_OFFSETR0 << 0 | \
299 CTRL_OFFSETR1 << 8 | \
300 CTRL_OFFSETR2 << 16 | \
302 #define PHY_CON4_RESET_VAL 0x08080808
304 #define CTRL_OFFSETW0 0x7F
305 #define CTRL_OFFSETW1 0x7F
306 #define CTRL_OFFSETW2 0x7F
307 #define CTRL_OFFSETW3 0x7F
308 #define PHY_CON6_VAL (CTRL_OFFSETW0 << 0 | \
309 CTRL_OFFSETW1 << 8 | \
310 CTRL_OFFSETW2 << 16 | \
312 #define PHY_CON6_RESET_VAL 0x08080808
314 #define PHY_CON14_RESET_VAL 0x001F0000
315 #define CTRL_PULLD_DQS 0xF
316 #define CTRL_PULLD_DQS_OFFSET 0
318 /* ZQ Configurations */
319 #define PHY_CON16_RESET_VAL 0x08000304
321 #define ZQ_CLK_EN (1 << 27)
322 #define ZQ_CLK_DIV_EN (1 << 18)
323 #define ZQ_MANUAL_STR (1 << 1)
324 #define ZQ_DONE (1 << 0)
325 #define ZQ_MODE_DDS_OFFSET 24
327 #define CTRL_RDLVL_GATE_ENABLE 1
328 #define CTRL_RDLVL_GATE_DISABLE 0
329 #define CTRL_RDLVL_DATA_ENABLE 2
332 #define DIRECT_CMD_NOP 0x07000000
333 #define DIRECT_CMD_PALL 0x01000000
334 #define DIRECT_CMD_ZQINIT 0x0a000000
335 #define DIRECT_CMD_CHANNEL_SHIFT 28
336 #define DIRECT_CMD_CHIP_SHIFT 20
337 #define DIRECT_CMD_BANK_SHIFT 16
338 #define DIRECT_CMD_REFA (5 << 24)
339 #define DIRECT_CMD_MRS1 0x71C00
340 #define DIRECT_CMD_MRS2 0x10BFC
341 #define DIRECT_CMD_MRS3 0x0050C
342 #define DIRECT_CMD_MRS4 0x00868
343 #define DIRECT_CMD_MRS5 0x00C04
346 #define IMPEDANCE_48_OHM 4
347 #define IMPEDANCE_40_OHM 5
348 #define IMPEDANCE_34_OHM 6
349 #define IMPEDANCE_30_OHM 7
350 #define PHY_CON39_VAL_48_OHM 0x09240924
351 #define PHY_CON39_VAL_40_OHM 0x0B6D0B6D
352 #define PHY_CON39_VAL_34_OHM 0x0DB60DB6
353 #define PHY_CON39_VAL_30_OHM 0x0FFF0FFF
355 #define CTRL_BSTLEN_OFFSET 8
356 #define CTRL_RDLAT_OFFSET 0
358 #define CMD_DEFAULT_LPDDR3 0xF
359 #define CMD_DEFUALT_OFFSET 0
360 #define T_WRDATA_EN 0x7
361 #define T_WRDATA_EN_DDR3 0x8
362 #define T_WRDATA_EN_OFFSET 16
363 #define T_WRDATA_EN_MASK 0x1f
365 #define PHY_CON31_VAL 0x0C183060
366 #define PHY_CON32_VAL 0x60C18306
367 #define PHY_CON33_VAL 0x00000030
369 #define PHY_CON31_RESET_VAL 0x0
370 #define PHY_CON32_RESET_VAL 0x0
371 #define PHY_CON33_RESET_VAL 0x0
373 #define SL_DLL_DYN_CON_EN (1 << 1)
374 #define FP_RESYNC (1 << 3)
375 #define CTRL_START (1 << 6)
377 #define DMC_AREF_EN (1 << 5)
378 #define DMC_CONCONTROL_EMPTY (1 << 8)
379 #define DFI_INIT_START (1 << 28)
381 #define DMC_MEMCONTROL_VAL 0x00312700
382 #define CLK_STOP_EN (1 << 0)
383 #define DPWRDN_EN (1 << 1)
384 #define DSREF_EN (1 << 5)
386 #define MEMBASECONFIG_CHIP_MASK_VAL 0x7E0
387 #define MEMBASECONFIG_CHIP_MASK_OFFSET 0
388 #define MEMBASECONFIG0_CHIP_BASE_VAL 0x20
389 #define MEMBASECONFIG1_CHIP_BASE_VAL 0x40
390 #define CHIP_BASE_OFFSET 16
392 #define MEMCONFIG_VAL 0x1323
393 #define PRECHCONFIG_DEFAULT_VAL 0xFF000000
394 #define PWRDNCONFIG_DEFAULT_VAL 0xFFFF00FF
396 #define TIMINGAREF_VAL 0x5d
397 #define TIMINGROW_VAL 0x345A8692
398 #define TIMINGDATA_VAL 0x3630065C
399 #define TIMINGPOWER_VAL 0x50380336
400 #define DFI_INIT_COMPLETE (1 << 3)
402 #define BRBRSVCONTROL_VAL 0x00000033
403 #define BRBRSVCONFIG_VAL 0x88778877
405 /* Clock Gating Control (CGCONTROL) register */
406 #define MEMIF_CG_EN (1 << 3) /* Memory interface clock gating */
407 #define SCG_CG_EN (1 << 2) /* Scheduler clock gating */
408 #define BUSIF_WR_CG_EN (1 << 1) /* Bus interface write channel clock gating */
409 #define BUSIF_RD_CG_EN (1 << 0) /* Bus interface read channel clock gating */
410 #define DMC_INTERNAL_CG (MEMIF_CG_EN | SCG_CG_EN | \
411 BUSIF_WR_CG_EN | BUSIF_RD_CG_EN)
413 /* DMC PHY Control0 register */
414 #define PHY_CONTROL0_RESET_VAL 0x0
415 #define MEM_TERM_EN (1 << 31) /* Termination enable for memory */
416 #define PHY_TERM_EN (1 << 30) /* Termination enable for PHY */
417 #define DMC_CTRL_SHGATE (1 << 29) /* Duration of DQS gating signal */
418 #define FP_RSYNC (1 << 3) /* Force DLL resyncronization */
420 /* Driver strength for CK, CKE, CS & CA */
421 #define IMP_OUTPUT_DRV_40_OHM 0x5
422 #define IMP_OUTPUT_DRV_30_OHM 0x7
423 #define DA_3_DS_OFFSET 25
424 #define DA_2_DS_OFFSET 22
425 #define DA_1_DS_OFFSET 19
426 #define DA_0_DS_OFFSET 16
427 #define CA_CK_DRVR_DS_OFFSET 9
428 #define CA_CKE_DRVR_DS_OFFSET 6
429 #define CA_CS_DRVR_DS_OFFSET 3
430 #define CA_ADR_DRVR_DS_OFFSET 0
432 #define PHY_CON42_CTRL_BSTLEN_SHIFT 8
433 #define PHY_CON42_CTRL_RDLAT_SHIFT 0
436 * Definitions that differ with SoC's.
437 * Below is the part defining macros for Exynos5250.
438 * Else part introduces macros for Exynos5420.
440 #ifndef CONFIG_EXYNOS5420
443 #define APLL_CON1_VAL (0x00203800)
446 #define MPLL_CON1_VAL (0x00203800)
449 #define CPLL_CON1_VAL (0x00203800)
452 #define DPLL_CON1_VAL (NOT_AVAILABLE)
455 #define GPLL_CON1_VAL (0x00203800)
457 /* EPLL_CON1, CON2 */
458 #define EPLL_CON1_VAL 0x00000000
459 #define EPLL_CON2_VAL 0x00000080
461 /* VPLL_CON1, CON2 */
462 #define VPLL_CON1_VAL 0x00000000
463 #define VPLL_CON2_VAL 0x00000080
465 /* RPLL_CON1, CON2 */
466 #define RPLL_CON1_VAL NOT_AVAILABLE
467 #define RPLL_CON2_VAL NOT_AVAILABLE
470 #define BPLL_CON1_VAL 0x00203800
473 #define SPLL_CON1_VAL NOT_AVAILABLE
476 #define IPLL_CON1_VAL NOT_AVAILABLE
479 #define KPLL_CON1_VAL NOT_AVAILABLE
482 #define CLK_SRC_ISP_VAL NOT_AVAILABLE
483 #define CLK_DIV_ISP0_VAL 0x31
484 #define CLK_DIV_ISP1_VAL 0x0
487 #define CLK_SRC_FSYS0_VAL 0x66666
488 #define CLK_DIV_FSYS0_VAL 0x0BB00000
489 #define CLK_DIV_FSYS1_VAL NOT_AVAILABLE
490 #define CLK_DIV_FSYS2_VAL NOT_AVAILABLE
493 /* 0 = MOUTAPLL, 1 = SCLKMPLL */
494 #define MUX_HPM_SEL 0
495 #define MUX_CPU_SEL 0
496 #define MUX_APLL_SEL 1
498 #define CLK_SRC_CPU_VAL ((MUX_HPM_SEL << 20) \
499 | (MUX_CPU_SEL << 16) \
503 #define CLK_SRC_CDREX_VAL 0x1
506 #define CLK_DIV_CDREX0_VAL NOT_AVAILABLE
507 #define CLK_DIV_CDREX1_VAL NOT_AVAILABLE
509 /* CLK_DIV_CPU0_VAL */
510 #define CLK_DIV_CPU0_VAL NOT_AVAILABLE
512 #define MCLK_CDREX2_RATIO 0x0
513 #define ACLK_EFCON_RATIO 0x1
514 #define MCLK_DPHY_RATIO 0x1
515 #define MCLK_CDREX_RATIO 0x1
516 #define ACLK_C2C_200_RATIO 0x1
517 #define C2C_CLK_400_RATIO 0x1
518 #define PCLK_CDREX_RATIO 0x1
519 #define ACLK_CDREX_RATIO 0x1
521 #define CLK_DIV_CDREX_VAL ((MCLK_DPHY_RATIO << 24) \
522 | (C2C_CLK_400_RATIO << 6) \
523 | (PCLK_CDREX_RATIO << 4) \
524 | (ACLK_CDREX_RATIO))
527 #define MUX_ACLK_300_GSCL_SEL 0x0
528 #define MUX_ACLK_300_GSCL_MID_SEL 0x0
529 #define MUX_ACLK_400_G3D_MID_SEL 0x0
530 #define MUX_ACLK_333_SEL 0x0
531 #define MUX_ACLK_300_DISP1_SEL 0x0
532 #define MUX_ACLK_300_DISP1_MID_SEL 0x0
533 #define MUX_ACLK_200_SEL 0x0
534 #define MUX_ACLK_166_SEL 0x0
535 #define CLK_SRC_TOP0_VAL ((MUX_ACLK_300_GSCL_SEL << 25) \
536 | (MUX_ACLK_300_GSCL_MID_SEL << 24) \
537 | (MUX_ACLK_400_G3D_MID_SEL << 20) \
538 | (MUX_ACLK_333_SEL << 16) \
539 | (MUX_ACLK_300_DISP1_SEL << 15) \
540 | (MUX_ACLK_300_DISP1_MID_SEL << 14) \
541 | (MUX_ACLK_200_SEL << 12) \
542 | (MUX_ACLK_166_SEL << 8))
545 #define MUX_ACLK_400_G3D_SEL 0x1
546 #define MUX_ACLK_400_ISP_SEL 0x0
547 #define MUX_ACLK_400_IOP_SEL 0x0
548 #define MUX_ACLK_MIPI_HSI_TXBASE_SEL 0x0
549 #define MUX_ACLK_300_GSCL_MID1_SEL 0x0
550 #define MUX_ACLK_300_DISP1_MID1_SEL 0x0
551 #define CLK_SRC_TOP1_VAL ((MUX_ACLK_400_G3D_SEL << 28) \
552 |(MUX_ACLK_400_ISP_SEL << 24) \
553 |(MUX_ACLK_400_IOP_SEL << 20) \
554 |(MUX_ACLK_MIPI_HSI_TXBASE_SEL << 16) \
555 |(MUX_ACLK_300_GSCL_MID1_SEL << 12) \
556 |(MUX_ACLK_300_DISP1_MID1_SEL << 8))
559 #define MUX_GPLL_SEL 0x1
560 #define MUX_BPLL_USER_SEL 0x0
561 #define MUX_MPLL_USER_SEL 0x0
562 #define MUX_VPLL_SEL 0x1
563 #define MUX_EPLL_SEL 0x1
564 #define MUX_CPLL_SEL 0x1
565 #define VPLLSRC_SEL 0x0
566 #define CLK_SRC_TOP2_VAL ((MUX_GPLL_SEL << 28) \
567 | (MUX_BPLL_USER_SEL << 24) \
568 | (MUX_MPLL_USER_SEL << 20) \
569 | (MUX_VPLL_SEL << 16) \
570 | (MUX_EPLL_SEL << 12) \
571 | (MUX_CPLL_SEL << 8) \
574 #define MUX_ACLK_333_SUB_SEL 0x1
575 #define MUX_ACLK_400_SUB_SEL 0x1
576 #define MUX_ACLK_266_ISP_SUB_SEL 0x1
577 #define MUX_ACLK_266_GPS_SUB_SEL 0x0
578 #define MUX_ACLK_300_GSCL_SUB_SEL 0x1
579 #define MUX_ACLK_266_GSCL_SUB_SEL 0x1
580 #define MUX_ACLK_300_DISP1_SUB_SEL 0x1
581 #define MUX_ACLK_200_DISP1_SUB_SEL 0x1
582 #define CLK_SRC_TOP3_VAL ((MUX_ACLK_333_SUB_SEL << 24) \
583 | (MUX_ACLK_400_SUB_SEL << 20) \
584 | (MUX_ACLK_266_ISP_SUB_SEL << 16) \
585 | (MUX_ACLK_266_GPS_SUB_SEL << 12) \
586 | (MUX_ACLK_300_GSCL_SUB_SEL << 10) \
587 | (MUX_ACLK_266_GSCL_SUB_SEL << 8) \
588 | (MUX_ACLK_300_DISP1_SUB_SEL << 6) \
589 | (MUX_ACLK_200_DISP1_SUB_SEL << 4))
591 #define CLK_SRC_TOP4_VAL NOT_AVAILABLE
592 #define CLK_SRC_TOP5_VAL NOT_AVAILABLE
593 #define CLK_SRC_TOP6_VAL NOT_AVAILABLE
594 #define CLK_SRC_TOP7_VAL NOT_AVAILABLE
597 #define ACLK_300_DISP1_RATIO 0x2
598 #define ACLK_400_G3D_RATIO 0x0
599 #define ACLK_333_RATIO 0x0
600 #define ACLK_266_RATIO 0x2
601 #define ACLK_200_RATIO 0x3
602 #define ACLK_166_RATIO 0x1
603 #define ACLK_133_RATIO 0x1
604 #define ACLK_66_RATIO 0x5
606 #define CLK_DIV_TOP0_VAL ((ACLK_300_DISP1_RATIO << 28) \
607 | (ACLK_400_G3D_RATIO << 24) \
608 | (ACLK_333_RATIO << 20) \
609 | (ACLK_266_RATIO << 16) \
610 | (ACLK_200_RATIO << 12) \
611 | (ACLK_166_RATIO << 8) \
612 | (ACLK_133_RATIO << 4) \
616 #define ACLK_MIPI_HSI_TX_BASE_RATIO 0x3
617 #define ACLK_66_PRE_RATIO 0x1
618 #define ACLK_400_ISP_RATIO 0x1
619 #define ACLK_400_IOP_RATIO 0x1
620 #define ACLK_300_GSCL_RATIO 0x2
622 #define CLK_DIV_TOP1_VAL ((ACLK_MIPI_HSI_TX_BASE_RATIO << 28) \
623 | (ACLK_66_PRE_RATIO << 24) \
624 | (ACLK_400_ISP_RATIO << 20) \
625 | (ACLK_400_IOP_RATIO << 16) \
626 | (ACLK_300_GSCL_RATIO << 12))
628 #define CLK_DIV_TOP2_VAL NOT_AVAILABLE
630 /* PLL Lock Value Factor */
631 #define PLL_LOCK_FACTOR 250
632 #define PLL_X_LOCK_FACTOR 3000
640 /* SRC_CLOCK = SCLK_MPLL */
641 #define CLK_SRC_PERIC0_VAL ((PWM_SEL << 24) \
642 | (UART3_SEL << 12) \
648 /* SRC_CLOCK = SCLK_MPLL */
652 #define CLK_SRC_PERIC1_VAL ((SPI2_SEL << 24) \
657 #define UART5_RATIO 7
658 #define UART4_RATIO 7
659 #define UART3_RATIO 7
660 #define UART2_RATIO 7
661 #define UART1_RATIO 7
662 #define UART0_RATIO 7
664 #define CLK_DIV_PERIC0_VAL ((UART3_RATIO << 12) \
665 | (UART2_RATIO << 8) \
666 | (UART1_RATIO << 4) \
669 #define SPI1_RATIO 0x7
670 #define SPI0_RATIO 0xf
671 #define SPI1_SUB_RATIO 0x0
672 #define SPI0_SUB_RATIO 0x0
673 #define CLK_DIV_PERIC1_VAL ((SPI1_SUB_RATIO << 24) \
674 | ((SPI1_RATIO << 16) \
675 | (SPI0_SUB_RATIO << 8) \
676 | (SPI0_RATIO << 0)))
679 #define SPI2_RATIO 0xf
680 #define SPI2_SUB_RATIO 0x0
681 #define CLK_DIV_PERIC2_VAL ((SPI2_SUB_RATIO << 8) \
686 #define CLK_DIV_PERIC3_VAL (PWM_RATIO << 0)
690 #define CLK_DIV_PERIC4_VAL NOT_AVAILABLE
692 /* CLK_SRC_DISP1_0 */
693 #define CLK_SRC_DISP1_0_VAL 0x6
694 #define CLK_DIV_DISP1_0_VAL NOT_AVAILABLE
696 #define APLL_FOUT (1 << 0)
697 #define KPLL_FOUT NOT_AVAILABLE
699 #define CLK_DIV_CPERI1_VAL NOT_AVAILABLE
703 #define CPU_CONFIG_STATUS_OFFSET 0x80
704 #define CPU_RST_FLAG_VAL 0xFCBA0D10
705 #define PAD_RETENTION_DRAM_COREBLK_VAL 0x10000000
708 #define APLL_CON1_VAL (0x0020F300)
711 #define MPLL_CON1_VAL (0x0020F300)
715 #define CPLL_CON1_VAL 0x0020f300
718 #define DPLL_CON1_VAL (0x0020F300)
721 #define GPLL_CON1_VAL (NOT_AVAILABLE)
724 /* EPLL_CON1, CON2 */
725 #define EPLL_CON1_VAL 0x00000000
726 #define EPLL_CON2_VAL 0x00000080
728 /* VPLL_CON1, CON2 */
729 #define VPLL_CON1_VAL 0x0020f300
730 #define VPLL_CON2_VAL NOT_AVAILABLE
732 /* RPLL_CON1, CON2 */
733 #define RPLL_CON1_VAL 0x00000000
734 #define RPLL_CON2_VAL 0x00000080
737 #define BPLL_CON1_VAL 0x0020f300
740 #define SPLL_CON1_VAL 0x0020f300
743 #define IPLL_CON1_VAL 0x00000080
746 #define KPLL_CON1_VAL 0x200000
749 #define CLK_SRC_ISP_VAL 0x33366000
750 #define CLK_DIV_ISP0_VAL 0x13131300
751 #define CLK_DIV_ISP1_VAL 0xbb110202
755 #define CLK_SRC_FSYS0_VAL 0x33033300
756 #define CLK_DIV_FSYS0_VAL 0x0
757 #define CLK_DIV_FSYS1_VAL 0x04f13c4f
758 #define CLK_DIV_FSYS2_VAL 0x041d0000
761 /* 0 = MOUTAPLL, 1 = SCLKMPLL */
762 #define MUX_HPM_SEL 1
763 #define MUX_CPU_SEL 0
764 #define MUX_APLL_SEL 1
766 #define CLK_SRC_CPU_VAL ((MUX_HPM_SEL << 20) \
767 | (MUX_CPU_SEL << 16) \
771 #define CLK_SRC_CDREX_VAL 0x00000011
774 #define CLK_DIV_CDREX0_VAL 0x30010100
775 #define CLK_DIV_CDREX1_VAL 0x300
777 #define CLK_DIV_CDREX_VAL 0x17010100
779 /* CLK_DIV_CPU0_VAL */
780 #define CLK_DIV_CPU0_VAL 0x01440020
783 #define CLK_SRC_TOP0_VAL 0x12221222
784 #define CLK_SRC_TOP1_VAL 0x00100200
785 #define CLK_SRC_TOP2_VAL 0x11101000
786 #define CLK_SRC_TOP3_VAL 0x11111111
787 #define CLK_SRC_TOP4_VAL 0x11110111
788 #define CLK_SRC_TOP5_VAL 0x11111101
789 #define CLK_SRC_TOP6_VAL 0x11110111
790 #define CLK_SRC_TOP7_VAL 0x00022200
793 #define CLK_DIV_TOP0_VAL 0x23712311
794 #define CLK_DIV_TOP1_VAL 0x13100B00
795 #define CLK_DIV_TOP2_VAL 0x11101100
797 /* PLL Lock Value Factor */
798 #define PLL_LOCK_FACTOR 200
799 #define PLL_X_LOCK_FACTOR 3000
809 /* SRC_CLOCK = SCLK_RPLL */
810 #define CLK_SRC_PERIC0_VAL ((SPDIF_SEL << 28) \
812 | (UART4_SEL << 20) \
813 | (UART3_SEL << 16) \
814 | (UART2_SEL << 12) \
819 /* SRC_CLOCK = SCLK_EPLL */
826 #define CLK_SRC_PERIC1_VAL ((SPI2_SEL << 28) \
829 | (AUDIO2_SEL << 16) \
830 | (AUDIO2_SEL << 12) \
835 #define UART4_RATIO 9
836 #define UART3_RATIO 9
837 #define UART2_RATIO 9
838 #define UART1_RATIO 9
839 #define UART0_RATIO 9
841 #define CLK_DIV_PERIC0_VAL ((PWM_RATIO << 28) \
842 | (UART4_RATIO << 24) \
843 | (UART3_RATIO << 20) \
844 | (UART2_RATIO << 16) \
845 | (UART1_RATIO << 12) \
846 | (UART0_RATIO << 8))
848 #define SPI2_RATIO 0x1
849 #define SPI1_RATIO 0x1
850 #define SPI0_RATIO 0x1
851 #define CLK_DIV_PERIC1_VAL ((SPI2_RATIO << 28) \
852 | (SPI1_RATIO << 24) \
853 | (SPI0_RATIO << 20))
856 #define PCM2_RATIO 0x3
857 #define PCM1_RATIO 0x3
858 #define CLK_DIV_PERIC2_VAL ((PCM2_RATIO << 24) \
859 | (PCM1_RATIO << 16))
862 #define AUDIO2_RATIO 0x5
863 #define AUDIO1_RATIO 0x5
864 #define AUDIO0_RATIO 0x5
865 #define CLK_DIV_PERIC3_VAL ((AUDIO2_RATIO << 28) \
866 | (AUDIO1_RATIO << 24) \
867 | (AUDIO0_RATIO << 20))
870 #define SPI2_PRE_RATIO 0x2
871 #define SPI1_PRE_RATIO 0x2
872 #define SPI0_PRE_RATIO 0x2
873 #define CLK_DIV_PERIC4_VAL ((SPI2_PRE_RATIO << 24) \
874 | (SPI1_PRE_RATIO << 16) \
875 | (SPI0_PRE_RATIO << 8))
877 /* CLK_SRC_DISP1_0 */
878 #define CLK_SRC_DISP1_0_VAL 0x10666600
879 #define CLK_DIV_DISP1_0_VAL 0x01050211
881 #define APLL_FOUT (1 << 0)
882 #define KPLL_FOUT (1 << 0)
884 #define CLK_DIV_CPERI1_VAL 0x3f3f0000
889 /* Errors that we can encourter in low-level setup */
892 SETUP_ERR_RDLV_COMPLETE_TIMEOUT = -1,
893 SETUP_ERR_ZQ_CALIBRATION_FAILURE = -2,
897 * Memory variant specific initialization code for DDR3
899 * @param mem Memory timings for this memory type.
900 * @param reset Reset DDR PHY during initialization.
901 * @return 0 if ok, SETUP_ERR_... if there is a problem
903 int ddr3_mem_ctrl_init(struct mem_timings *mem, int reset);
905 /* Memory variant specific initialization code for LPDDR3 */
906 void lpddr3_mem_ctrl_init(void);
909 * Configure ZQ I/O interface
911 * @param mem Memory timings for this memory type.
912 * @param phy0_con16 Register address for dmc_phy0->phy_con16
913 * @param phy1_con16 Register address for dmc_phy1->phy_con16
914 * @param phy0_con17 Register address for dmc_phy0->phy_con17
915 * @param phy1_con17 Register address for dmc_phy1->phy_con17
916 * @return 0 if ok, -1 on error
918 int dmc_config_zq(struct mem_timings *mem, uint32_t *phy0_con16,
919 uint32_t *phy1_con16, uint32_t *phy0_con17,
920 uint32_t *phy1_con17);
922 * Send NOP and MRS/EMRS Direct commands
924 * @param mem Memory timings for this memory type.
925 * @param directcmd Register address for dmc_phy->directcmd
927 void dmc_config_mrs(struct mem_timings *mem, uint32_t *directcmd);
930 * Send PALL Direct commands
932 * @param mem Memory timings for this memory type.
933 * @param directcmd Register address for dmc_phy->directcmd
935 void dmc_config_prech(struct mem_timings *mem, uint32_t *directcmd);
938 * Reset the DLL. This function is common between DDR3 and LPDDR2.
939 * However, the reset value is different. So we are passing a flag
940 * ddr_mode to distinguish between LPDDR2 and DDR3.
942 * @param phycontrol0 Register address for dmc_phy->phycontrol0
943 * @param ddr_mode Type of DDR memory
945 void update_reset_dll(uint32_t *phycontrol0, enum ddr_mode);