1 // SPDX-License-Identifier: GPL-2.0+
3 * Miscelaneous DaVinci functions.
5 * Copyright (C) 2009 Nick Thompson, GE Fanuc Ltd, <nick.thompson@gefanuc.com>
6 * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
7 * Copyright (C) 2008 Lyrtech <www.lyrtech.com>
8 * Copyright (C) 2004 Texas Instruments.
16 #include <asm/arch/hardware.h>
18 #include <asm/arch/davinci_misc.h>
20 DECLARE_GLOBAL_DATA_PTR;
22 #ifndef CONFIG_SPL_BUILD
25 /* dram_init must store complete ramsize in gd->ram_size */
26 gd->ram_size = get_ram_size(
27 (void *)CONFIG_SYS_SDRAM_BASE,
28 CONFIG_MAX_RAM_BANK_SIZE);
32 int dram_init_banksize(void)
34 gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
35 gd->bd->bi_dram[0].size = gd->ram_size;
41 #ifdef CONFIG_DRIVER_TI_EMAC
43 * Read ethernet MAC address from EEPROM for DVEVM compatible boards.
44 * Returns 1 if found, 0 otherwise.
46 int dvevm_read_mac_address(uint8_t *buf)
48 #ifdef CONFIG_SYS_I2C_EEPROM_ADDR
49 /* Read MAC address. */
50 if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0x7F00,
51 CONFIG_SYS_I2C_EEPROM_ADDR_LEN, (uint8_t *) &buf[0], 6))
54 /* Check that MAC address is valid. */
55 if (!is_valid_ethaddr(buf))
61 printf("Read from EEPROM @ 0x%02x failed\n",
62 CONFIG_SYS_I2C_EEPROM_ADDR);
64 #endif /* CONFIG_SYS_I2C_EEPROM_ADDR */
70 * Set the mii mode as MII or RMII
72 void davinci_emac_mii_mode_sel(int mode_sel)
76 val = readl(&davinci_syscfg_regs->cfgchip3);
81 writel(val, &davinci_syscfg_regs->cfgchip3);
85 * If there is no MAC address in the environment, then it will be initialized
86 * (silently) from the value in the EEPROM.
88 void davinci_sync_env_enetaddr(uint8_t *rom_enetaddr)
90 uint8_t env_enetaddr[6];
93 ret = eth_env_get_enetaddr_by_index("eth", 0, env_enetaddr);
96 * There is no MAC address in the environment, so we
97 * initialize it from the value in the EEPROM.
99 debug("### Setting environment from EEPROM MAC address = "
102 ret = !eth_env_set_enetaddr("ethaddr", rom_enetaddr);
105 printf("Failed to set mac address from EEPROM: %d\n", ret);
107 #endif /* CONFIG_DRIVER_TI_EMAC */
112 * Mask all IRQs by clearing the global enable and setting
113 * the enable clear for all the 90 interrupts.
115 writel(0, &davinci_aintc_regs->ger);
117 writel(0, &davinci_aintc_regs->hier);
119 writel(0xffffffff, &davinci_aintc_regs->ecr1);
120 writel(0xffffffff, &davinci_aintc_regs->ecr2);
121 writel(0xffffffff, &davinci_aintc_regs->ecr3);
125 * Enable PSC for various peripherals.
127 int da8xx_configure_lpsc_items(const struct lpsc_resource *item,
132 for (i = 0; i < n_items; i++)
133 lpsc_on(item[i].lpsc_no);