1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Low-level board setup code for TI DaVinci SoC based boards.
5 * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
7 * Partially based on TI sources, original copyrights follow:
11 * Board specific setup info
14 * Texas Instruments, <www.ti.com>
15 * Kshitij Gupta <Kshitij@ti.com>
17 * Modified for OMAP 1610 H2 board by Nishant Kamat, Jan 2004
19 * Modified for OMAP 5912 OSK board by Rishi Bhattacharya, Apr 2004
21 * Modified for DV-EVM board by Rishi Bhattacharya, Apr 2005
23 * Modified for DV-EVM board by Swaminathan S, Nov 2005
28 #define MDSTAT_STATE 0x3f
32 #ifdef CONFIG_SOC_DM644X
34 /*-------------------------------------------------------*
35 * Mask all IRQs by setting all bits in the EINT default *
36 *-------------------------------------------------------*/
43 /*------------------------------------------------------*
44 * Put the GEM in reset *
45 *------------------------------------------------------*/
47 /* Put the GEM in reset */
48 ldr r8, PSC_GEM_FLAG_CLEAR
54 /* Enable the Power Domain Transition Command */
60 /* Check for Transition Complete(PTSTAT) */
65 bne checkStatClkStopGem
67 /* Check for GEM Reset Completion */
72 bne checkGemStatClkStop
74 /* Do this for enabling a WDT initiated reset this is a workaround
75 for a chip bug. Not required under normal situations */
80 /*------------------------------------------------------*
81 * Enable L1 & L2 Memories in Fast mode *
82 *------------------------------------------------------*/
88 ldr r10, MMARG_BRF0_VAL
95 /*------------------------------------------------------*
96 * DDR2 PLL Initialization *
97 *------------------------------------------------------*/
99 /* Select the Clock Mode Depending on the Value written in the Boot Table by the run script */
102 ldr r7, PLL_CLKSRC_MASK
109 /* Select the PLLEN source */
110 ldr r7, PLL_ENSRC_MASK
115 ldr r7, PLL_BYPASS_MASK
119 /* Wait for few cycles to allow PLLEN Mux switch properly to bypass Clock */
126 ldr r7, PLL_RESET_MASK
130 /* Power up the PLL */
131 ldr r7, PLL_PWRUP_MASK
135 /* Enable the PLL from Disable Mode */
136 ldr r7, PLL_DISABLE_ENABLE_MASK
140 /* Program the PLL Multiplier */
142 mov r2, $0x17 /* 162 MHz */
145 /* Program the PLL2 Divisor Value */
150 /* Program the PLL2 Divisor Value */
152 mov r4, $0x0b /* 54 MHz */
156 ldr r8, PLL2_DIV_MASK
165 /* Program the GOSET bit to take new divider values */
179 ldr r8, PLL2_DIV_MASK
188 /* Program the GOSET bit to take new divider values */
201 /* Wait for PLL to Reset Properly */
207 /* Bring PLL out of Reset */
213 /* Wait for PLL to Lock */
214 ldr r10, PLL_LOCK_COUNT
225 /*------------------------------------------------------*
226 * Issue Soft Reset to DDR Module *
227 *------------------------------------------------------*/
229 /* Shut down the DDR2 LPSC Module */
230 ldr r8, PSC_FLAG_CLEAR
237 /* Enable the Power Domain Transition Command */
243 /* Check for Transition Complete(PTSTAT) */
250 /* Check for DDR2 Controller Enable Completion */
254 and r7, r7, $MDSTAT_STATE
256 bne checkDDRStatClkStop
258 /*------------------------------------------------------*
259 * Program DDR2 MMRs for 162MHz Setting *
260 *------------------------------------------------------*/
262 /* Program PHY Control Register */
267 /* Program SDRAM Bank Config Register */
272 /* Program SDRAM TIM-0 Config Register */
274 ldr r7, SDTIM0_VAL_162MHz
277 /* Program SDRAM TIM-1 Config Register */
279 ldr r7, SDTIM1_VAL_162MHz
282 /* Program the SDRAM Bank Config Control Register */
289 /* Program SDRAM SDREF Config Register */
294 /*------------------------------------------------------*
295 * Issue Soft Reset to DDR Module *
296 *------------------------------------------------------*/
298 /* Issue a Dummy DDR2 read/write */
299 ldr r8, DDR2_START_ADDR
304 /* Shut down the DDR2 LPSC Module */
305 ldr r8, PSC_FLAG_CLEAR
312 /* Enable the Power Domain Transition Command */
318 /* Check for Transition Complete(PTSTAT) */
323 bne checkStatClkStop2
325 /* Check for DDR2 Controller Enable Completion */
326 checkDDRStatClkStop2:
329 and r7, r7, $MDSTAT_STATE
331 bne checkDDRStatClkStop2
333 /*------------------------------------------------------*
334 * Turn DDR2 Controller Clocks On *
335 *------------------------------------------------------*/
337 /* Enable the DDR2 LPSC Module */
343 /* Enable the Power Domain Transition Command */
349 /* Check for Transition Complete(PTSTAT) */
356 /* Check for DDR2 Controller Enable Completion */
360 and r7, r7, $MDSTAT_STATE
362 bne checkDDRStatClkEn2
364 /* DDR Writes and Reads */
369 /*------------------------------------------------------*
370 * System PLL Initialization *
371 *------------------------------------------------------*/
373 /* Select the Clock Mode Depending on the Value written in the Boot Table by the run script */
376 ldr r7, PLL_CLKSRC_MASK
383 /* Select the PLLEN source */
384 ldr r7, PLL_ENSRC_MASK
389 ldr r7, PLL_BYPASS_MASK
393 /* Wait for few cycles to allow PLLEN Mux switch properly to bypass Clock */
401 ldr r7, PLL_RESET_MASK
405 /* Disable the PLL */
409 /* Power up the PLL */
410 ldr r7, PLL_PWRUP_MASK
414 /* Enable the PLL from Disable Mode */
415 ldr r7, PLL_DISABLE_ENABLE_MASK
419 /* Program the PLL Multiplier */
421 mov r3, $0x15 /* For 594MHz */
424 /* Wait for PLL to Reset Properly */
431 /* Bring PLL out of Reset */
436 /* Wait for PLL to Lock */
437 ldr r10, PLL_LOCK_COUNT
452 /*------------------------------------------------------*
453 * AEMIF configuration for NOR Flash (double check) *
454 *------------------------------------------------------*/
483 /*--------------------------------------*
484 * VTP manual Calibration *
485 *--------------------------------------*/
494 /* Wait for 33 VTP CLK cycles. VRP operates at 27 MHz */
495 ldr r10, VTP_LOCK_COUNT
506 mov r8, r7, LSL #32-10
507 mov r8, r8, LSR #32-10 /* grab low 10 bits */
515 /* Wait for 33 VTP CLK cycles. VRP operates at 27 MHz */
516 ldr r10, VTP_LOCK_COUNT
531 * Call board-specific lowlevel init.
532 * That MUST be present and THAT returns
533 * back to arch calling code with "mov pc, lr."
540 .word 0x01c40000 /* Device Configuration Registers */
542 .word 0x01c40004 /* Device Configuration Registers */
584 /* DDR2 MMR & CONFIGURATION VALUES, 162 MHZ clock */
598 #elif defined DDR_8BANKS
601 #error "Unknown DDR configuration!!!"
612 .word 0x200000f0 /* VTP IO Control register */
614 .word 0x01c42030 /* DDR VPTR MMR */
634 /* GEM Power Up & LPSC Control Register */
640 /* For WDT reset chip bug */
645 .word 0xfffffeff /* Mask the Clock Mode bit */
647 .word 0xffffffdf /* Select the PLLEN source */
649 .word 0xfffffffe /* Put the PLL in BYPASS */
651 .word 0xfffffff7 /* Put the PLL in Reset Mode */
653 .word 0xfffffffd /* PLL Power up Mask Bit */
654 PLL_DISABLE_ENABLE_MASK:
655 .word 0xffffffef /* Enable the PLL from Disable */
659 /* PLL1-SYSTEM PLL MMRs */
665 /* PLL2-SYSTEM PLL MMRs */
682 .word 0x01c42010 /* BRF margin mode 0 (R/W)*/
690 #else /* CONFIG_SOC_DM644X */