1 /* SPDX-License-Identifier: GPL-2.0+ */
4 * Heiko Schocher, DENX Software Engineering, hs@denx.de.
6 #ifndef _DV_PLL_DEFS_H_
7 #define _DV_PLL_DEFS_H_
10 unsigned int pid; /* 0x00 */
11 unsigned char rsvd0[224]; /* 0x04 */
12 unsigned int rstype; /* 0xe4 */
13 unsigned char rsvd1[24]; /* 0xe8 */
14 unsigned int pllctl; /* 0x100 */
15 unsigned char rsvd2[4]; /* 0x104 */
16 unsigned int secctl; /* 0x108 */
17 unsigned int rv; /* 0x10c */
18 unsigned int pllm; /* 0x110 */
19 unsigned int prediv; /* 0x114 */
20 unsigned int plldiv1; /* 0x118 */
21 unsigned int plldiv2; /* 0x11c */
22 unsigned int plldiv3; /* 0x120 */
23 unsigned int oscdiv1; /* 0x124 */
24 unsigned int postdiv; /* 0x128 */
25 unsigned int bpdiv; /* 0x12c */
26 unsigned char rsvd5[8]; /* 0x130 */
27 unsigned int pllcmd; /* 0x138 */
28 unsigned int pllstat; /* 0x13c */
29 unsigned int alnctl; /* 0x140 */
30 unsigned int dchange; /* 0x144 */
31 unsigned int cken; /* 0x148 */
32 unsigned int ckstat; /* 0x14c */
33 unsigned int systat; /* 0x150 */
34 unsigned char rsvd6[12]; /* 0x154 */
35 unsigned int plldiv4; /* 0x160 */
36 unsigned int plldiv5; /* 0x164 */
37 unsigned int plldiv6; /* 0x168 */
38 unsigned int plldiv7; /* 0x16C */
39 unsigned int plldiv8; /* 0x170 */
40 unsigned int plldiv9; /* 0x174 */
43 #define PLL_MASTER_LOCK (1 << 4)
45 #define PLLCTL_CLOCK_MODE_SHIFT 8
46 #define PLLCTL_PLLEN (1 << 0)
47 #define PLLCTL_PLLPWRDN (1 << 1)
48 #define PLLCTL_PLLRST (1 << 3)
49 #define PLLCTL_PLLDIS (1 << 4)
50 #define PLLCTL_PLLENSRC (1 << 5)
51 #define PLLCTL_RES_9 (1 << 8)
52 #define PLLCTL_EXTCLKSRC (1 << 9)
54 #define PLL_DIVEN (1 << 15)
55 #define PLL_POSTDEN PLL_DIVEN
57 #define PLL_SCSCFG3_DIV45PENA (1 << 2)
58 #define PLL_SCSCFG3_EMA_CLKSRC (1 << 1)
60 #define PLL_RSTYPE_POR (1 << 0)
61 #define PLL_RSTYPE_XWRST (1 << 1)
63 #define PLLSECCTL_TINITZ (1 << 16)
64 #define PLLSECCTL_TENABLE (1 << 17)
65 #define PLLSECCTL_TENABLEDIV (1 << 18)
66 #define PLLSECCTL_STOPMODE (1 << 22)
68 #define PLLCMD_GOSET (1 << 0)
69 #define PLLCMD_GOSTAT (1 << 0)
71 #define PLL0_LOCK 0x07000000
72 #define PLL1_LOCK 0x07000000
74 #define dv_pll0_regs ((struct dv_pll_regs *)DAVINCI_PLL_CNTRL0_BASE)
75 #define dv_pll1_regs ((struct dv_pll_regs *)DAVINCI_PLL_CNTRL1_BASE)
77 #define ARM_PLLDIV (offsetof(struct dv_pll_regs, plldiv2))
78 #define DDR_PLLDIV (offsetof(struct dv_pll_regs, plldiv7))
79 #define SPI_PLLDIV (offsetof(struct dv_pll_regs, plldiv4))
81 unsigned int davinci_clk_get(unsigned int div);
82 #endif /* _DV_PLL_DEFS_H_ */