1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
7 * ----------------------------------------------------------------------------
11 * TI DaVinci (DM644X) EMAC peripheral driver header for DV-EVM
13 * Copyright (C) 2005 Texas Instruments.
15 * ----------------------------------------------------------------------------
18 * ver. 1.0: Sep 2005, TI PSP Team - Created EMAC version for uBoot.
21 #ifndef _DM644X_EMAC_H_
22 #define _DM644X_EMAC_H_
24 #include <asm/arch/hardware.h>
26 #ifdef CONFIG_SOC_DM365
27 #define EMAC_BASE_ADDR (0x01d07000)
28 #define EMAC_WRAPPER_BASE_ADDR (0x01d0a000)
29 #define EMAC_WRAPPER_RAM_ADDR (0x01d08000)
30 #define EMAC_MDIO_BASE_ADDR (0x01d0b000)
31 #define DAVINCI_EMAC_VERSION2
32 #elif defined(CONFIG_SOC_DA8XX)
33 #define EMAC_BASE_ADDR DAVINCI_EMAC_CNTRL_REGS_BASE
34 #define EMAC_WRAPPER_BASE_ADDR DAVINCI_EMAC_WRAPPER_CNTRL_REGS_BASE
35 #define EMAC_WRAPPER_RAM_ADDR DAVINCI_EMAC_WRAPPER_RAM_BASE
36 #define EMAC_MDIO_BASE_ADDR DAVINCI_MDIO_CNTRL_REGS_BASE
37 #define DAVINCI_EMAC_VERSION2
39 #define EMAC_BASE_ADDR (0x01c80000)
40 #define EMAC_WRAPPER_BASE_ADDR (0x01c81000)
41 #define EMAC_WRAPPER_RAM_ADDR (0x01c82000)
42 #define EMAC_MDIO_BASE_ADDR (0x01c84000)
45 #ifdef CONFIG_SOC_DM646X
46 #define DAVINCI_EMAC_VERSION2
47 #define DAVINCI_EMAC_GIG_ENABLE
50 #ifdef CONFIG_SOC_DM646X
51 /* MDIO module input frequency */
52 #define EMAC_MDIO_BUS_FREQ 76500000
53 /* MDIO clock output frequency */
54 #define EMAC_MDIO_CLOCK_FREQ 2500000 /* 2.5 MHz */
55 #elif defined(CONFIG_SOC_DM365)
56 /* MDIO module input frequency */
57 #define EMAC_MDIO_BUS_FREQ 121500000
58 /* MDIO clock output frequency */
59 #define EMAC_MDIO_CLOCK_FREQ 2200000 /* 2.2 MHz */
60 #elif defined(CONFIG_SOC_DA8XX)
61 /* MDIO module input frequency */
62 #define EMAC_MDIO_BUS_FREQ clk_get(DAVINCI_MDIO_CLKID)
63 /* MDIO clock output frequency */
64 #define EMAC_MDIO_CLOCK_FREQ 2000000 /* 2.0 MHz */
66 /* MDIO module input frequency */
67 #define EMAC_MDIO_BUS_FREQ 99000000 /* PLL/6 - 99 MHz */
68 /* MDIO clock output frequency */
69 #define EMAC_MDIO_CLOCK_FREQ 2000000 /* 2.0 MHz */
72 #define PHY_KSZ8873 (0x00221450)
73 int ksz8873_is_phy_connected(int phy_addr);
74 int ksz8873_get_link_speed(int phy_addr);
75 int ksz8873_init_phy(int phy_addr);
76 int ksz8873_auto_negotiate(int phy_addr);
78 #define PHY_LXT972 (0x001378e2)
79 int lxt972_is_phy_connected(int phy_addr);
80 int lxt972_get_link_speed(int phy_addr);
81 int lxt972_init_phy(int phy_addr);
82 int lxt972_auto_negotiate(int phy_addr);
84 #define PHY_DP83848 (0x20005c90)
85 int dp83848_is_phy_connected(int phy_addr);
86 int dp83848_get_link_speed(int phy_addr);
87 int dp83848_init_phy(int phy_addr);
88 int dp83848_auto_negotiate(int phy_addr);
90 #define PHY_ET1011C (0x282f013)
91 int et1011c_get_link_speed(int phy_addr);
93 #endif /* _DM644X_EMAC_H_ */