arch/arm/mach-davinci/cpu.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2004 Texas Instruments.
   4  * Copyright (C) 2009 David Brownell
   5  */
   6
   7 #include <common.h>
   8 #include <asm/arch/hardware.h>
   9 #include <asm/io.h>
  10
  11 DECLARE_GLOBAL_DATA_PTR;
  12
  13 /* offsets from PLL controller base */
  14 #define PLLC_PLLCTL     0x100
  15 #define PLLC_PLLM       0x110
  16 #define PLLC_PREDIV     0x114
  17 #define PLLC_PLLDIV1    0x118
  18 #define PLLC_PLLDIV2    0x11c
  19 #define PLLC_PLLDIV3    0x120
  20 #define PLLC_POSTDIV    0x128
  21 #define PLLC_BPDIV      0x12c
  22 #define PLLC_PLLDIV4    0x160
  23 #define PLLC_PLLDIV5    0x164
  24 #define PLLC_PLLDIV6    0x168
  25 #define PLLC_PLLDIV7    0x16c
  26 #define PLLC_PLLDIV8    0x170
  27 #define PLLC_PLLDIV9    0x174
  28
  29 unsigned int sysdiv[9] = {
  30         PLLC_PLLDIV1, PLLC_PLLDIV2, PLLC_PLLDIV3, PLLC_PLLDIV4, PLLC_PLLDIV5,
  31         PLLC_PLLDIV6, PLLC_PLLDIV7, PLLC_PLLDIV8, PLLC_PLLDIV9
  32 };
  33
  34 int clk_get(enum davinci_clk_ids id)
  35 {
  36         int pre_div;
  37         int pllm;
  38         int post_div;
  39         int pll_out;
  40         unsigned int pll_base;
  41
  42         pll_out = CONFIG_SYS_OSCIN_FREQ;
  43
  44         if (id == DAVINCI_AUXCLK_CLKID)
  45                 goto out;
  46
  47         if ((id >> 16) == 1)
  48                 pll_base = (unsigned int)davinci_pllc1_regs;
  49         else
  50                 pll_base = (unsigned int)davinci_pllc0_regs;
  51
  52         id &= 0xFFFF;
  53
  54         /*
  55          * Lets keep this simple. Combining operations can result in
  56          * unexpected approximations
  57          */
  58         pre_div = (readl(pll_base + PLLC_PREDIV) &
  59                 DAVINCI_PLLC_DIV_MASK) + 1;
  60         pllm = readl(pll_base + PLLC_PLLM) + 1;
  61
  62         pll_out /= pre_div;
  63         pll_out *= pllm;
  64
  65         if (id == DAVINCI_PLLM_CLKID)
  66                 goto out;
  67
  68         post_div = (readl(pll_base + PLLC_POSTDIV) &
  69                 DAVINCI_PLLC_DIV_MASK) + 1;
  70
  71         pll_out /= post_div;
  72
  73         if (id == DAVINCI_PLLC_CLKID)
  74                 goto out;
  75
  76         pll_out /= (readl(pll_base + sysdiv[id - 1]) &
  77                 DAVINCI_PLLC_DIV_MASK) + 1;
  78
  79 out:
  80         return pll_out;
  81 }
  82
  83 int set_cpu_clk_info(void)
  84 {
  85         gd->bd->bi_arm_freq = clk_get(DAVINCI_ARM_CLKID) / 1000000;
  86         /* DDR PHY uses an x2 input clock */
  87         gd->bd->bi_ddr_freq = cpu_is_da830() ? 0 :
  88                                 (clk_get(DAVINCI_DDR_CLKID) / 1000000);
  89         gd->bd->bi_dsp_freq = 0;
  90         return 0;
  91 }