4 prompt "DaVinci board select"
9 select MACH_DAVINCI_DA850_EVM
13 config TARGET_OMAPL138_LCDK
20 bool "LEGO MINDSTORMS EV3"
21 select MACH_DAVINCI_DA850_EVM
30 bool "Enable Lowlevel DA850 initialization"
33 config SYS_DA850_PLL_INIT
36 config SYS_DA850_DDR_INIT
45 select SYS_DA850_DDR_INIT if SUPPORT_SPL || DA850_LOWLEVEL
46 select SYS_DA850_PLL_INIT if SUPPORT_SPL || DA850_LOWLEVEL
48 config MACH_DAVINCI_DA850_EVM
52 comment "DA850 PLL Initialization Parameters"
55 int "PLLCTL Clock Mode"
58 Set PLLCTL Clock Mode bit as External Clock or On Chip oscillator
60 config SYS_DA850_PLL0_POSTDIV
61 int "PLLC0 PLL Post-Divider"
64 Value written to PLLC0 PLL Post-Divider Control Register
66 config SYS_DA850_PLL0_PLLDIV1
70 Value written to PLLC0 Divider 1 register
72 config SYS_DA850_PLL0_PLLDIV2
76 Value written to PLLC0 Divider 2 register
78 config SYS_DA850_PLL0_PLLDIV3
82 Value written to PLLC0 Divider 3 register
84 config SYS_DA850_PLL0_PLLDIV4
88 Value written to PLLC0 Divider 4 register
90 config SYS_DA850_PLL0_PLLDIV5
94 Value written to PLLC0 Divider 5 register
96 config SYS_DA850_PLL0_PLLDIV6
100 Value written to PLLC0 Divider 6 register
102 config SYS_DA850_PLL0_PLLDIV7
103 hex "PLLC0 Divider 7"
106 Value written to PLLC0 Divider 7 register
108 config SYS_DA850_PLL1_POSTDIV
109 hex "PLLC1 PLL Post-Divider"
112 Value written to PLLC1 PLL Post-Divider Control Register
114 config SYS_DA850_PLL1_PLLDIV1
115 hex "PLLC1 Divider 2"
118 Value written to PLLC1 Divider 1 register
120 config SYS_DA850_PLL1_PLLDIV2
121 hex "PLLC1 Divider 2"
124 Value written to PLLC1 Divider 2 register
126 config SYS_DA850_PLL1_PLLDIV3
127 hex "PLLC1 Divider 3"
130 Value written to PLLC1 Divider 3 register
134 source "board/davinci/da8xxevm/Kconfig"
135 source "board/lego/ev3/Kconfig"
138 default "board/$(BOARDDIR)/u-boot-spl-da850evm.lds"