1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * (C) Copyright 2012,2015 Stephen Warren
6 #ifndef _BCM2835_MBOX_H
7 #define _BCM2835_MBOX_H
9 #include <linux/compiler.h>
12 * The BCM2835 SoC contains (at least) two CPUs; the VideoCore (a/k/a "GPU")
13 * and the ARM CPU. The ARM CPU is often thought of as the main CPU.
14 * However, the VideoCore actually controls the initial SoC boot, and hides
15 * much of the hardware behind a protocol. This protocol is transported
16 * using the SoC's mailbox hardware module.
18 * The mailbox hardware supports passing 32-bit values back and forth.
19 * Presumably by software convention of the firmware, the bottom 4 bits of the
20 * value are used to indicate a logical channel, and the upper 28 bits are the
21 * actual payload. Various channels exist using these simple raw messages. See
22 * https://github.com/raspberrypi/firmware/wiki/Mailboxes for a list. As an
23 * example, the messages on the power management channel are a bitmask of
24 * devices whose power should be enabled.
26 * The property mailbox channel passes messages that contain the (16-byte
27 * aligned) ARM physical address of a memory buffer. This buffer is passed to
28 * the VC for processing, is modified in-place by the VC, and the address then
29 * passed back to the ARM CPU as the response mailbox message to indicate
30 * request completion. The buffers have a generic and extensible format; each
31 * buffer contains a standard header, a list of "tags", and a terminating zero
32 * entry. Each tag contains an ID indicating its type, and length fields for
33 * generic parsing. With some limitations, an arbitrary set of tags may be
34 * combined together into a single message buffer. This file defines structs
35 * representing the header and many individual tag layouts and IDs.
40 #ifndef CONFIG_BCM2835
41 #define BCM2835_MBOX_PHYSADDR 0x3f00b880
43 #define BCM2835_MBOX_PHYSADDR 0x2000b880
46 struct bcm2835_mbox_regs {
57 #define BCM2835_MBOX_STATUS_WR_FULL 0x80000000
58 #define BCM2835_MBOX_STATUS_RD_EMPTY 0x40000000
60 /* Lower 4-bits are channel ID */
61 #define BCM2835_CHAN_MASK 0xf
62 #define BCM2835_MBOX_PACK(chan, data) (((data) & (~BCM2835_CHAN_MASK)) | \
63 (chan & BCM2835_CHAN_MASK))
64 #define BCM2835_MBOX_UNPACK_CHAN(val) ((val) & BCM2835_CHAN_MASK)
65 #define BCM2835_MBOX_UNPACK_DATA(val) ((val) & (~BCM2835_CHAN_MASK))
67 /* Property mailbox buffer structures */
69 #define BCM2835_MBOX_PROP_CHAN 8
71 /* All message buffers must start with this header */
72 struct bcm2835_mbox_hdr {
77 #define BCM2835_MBOX_REQ_CODE 0
78 #define BCM2835_MBOX_RESP_CODE_SUCCESS 0x80000000
80 #define BCM2835_MBOX_INIT_HDR(_m_) { \
81 memset((_m_), 0, sizeof(*(_m_))); \
82 (_m_)->hdr.buf_size = sizeof(*(_m_)); \
83 (_m_)->hdr.code = 0; \
88 * A message buffer contains a list of tags. Each tag must also start with
89 * a standardized header.
91 struct bcm2835_mbox_tag_hdr {
97 #define BCM2835_MBOX_INIT_TAG(_t_, _id_) { \
98 (_t_)->tag_hdr.tag = BCM2835_MBOX_TAG_##_id_; \
99 (_t_)->tag_hdr.val_buf_size = sizeof((_t_)->body); \
100 (_t_)->tag_hdr.val_len = sizeof((_t_)->body.req); \
103 #define BCM2835_MBOX_INIT_TAG_NO_REQ(_t_, _id_) { \
104 (_t_)->tag_hdr.tag = BCM2835_MBOX_TAG_##_id_; \
105 (_t_)->tag_hdr.val_buf_size = sizeof((_t_)->body); \
106 (_t_)->tag_hdr.val_len = 0; \
109 /* When responding, the VC sets this bit in val_len to indicate a response */
110 #define BCM2835_MBOX_TAG_VAL_LEN_RESPONSE 0x80000000
113 * Below we define the ID and struct for many possible tags. This header only
114 * defines individual tag structs, not entire message structs, since in
115 * general an arbitrary set of tags may be combined into a single message.
116 * Clients of the mbox API are expected to define their own overall message
117 * structures by combining the header, a set of tags, and a terminating
118 * entry. For example,
121 * struct bcm2835_mbox_hdr hdr;
122 * struct bcm2835_mbox_tag_get_arm_mem get_arm_mem;
123 * ... perhaps other tags here ...
128 #define BCM2835_MBOX_TAG_GET_BOARD_REV 0x00010002
130 struct bcm2835_mbox_tag_get_board_rev {
131 struct bcm2835_mbox_tag_hdr tag_hdr;
141 #define BCM2835_MBOX_TAG_GET_MAC_ADDRESS 0x00010003
143 struct bcm2835_mbox_tag_get_mac_address {
144 struct bcm2835_mbox_tag_hdr tag_hdr;
155 #define BCM2835_MBOX_TAG_GET_BOARD_SERIAL 0x00010004
157 struct bcm2835_mbox_tag_get_board_serial {
158 struct bcm2835_mbox_tag_hdr tag_hdr;
166 #define BCM2835_MBOX_TAG_GET_ARM_MEMORY 0x00010005
168 struct bcm2835_mbox_tag_get_arm_mem {
169 struct bcm2835_mbox_tag_hdr tag_hdr;
180 #define BCM2835_MBOX_POWER_DEVID_SDHCI 0
181 #define BCM2835_MBOX_POWER_DEVID_UART0 1
182 #define BCM2835_MBOX_POWER_DEVID_UART1 2
183 #define BCM2835_MBOX_POWER_DEVID_USB_HCD 3
184 #define BCM2835_MBOX_POWER_DEVID_I2C0 4
185 #define BCM2835_MBOX_POWER_DEVID_I2C1 5
186 #define BCM2835_MBOX_POWER_DEVID_I2C2 6
187 #define BCM2835_MBOX_POWER_DEVID_SPI 7
188 #define BCM2835_MBOX_POWER_DEVID_CCP2TX 8
190 #define BCM2835_MBOX_POWER_STATE_RESP_ON (1 << 0)
191 /* Device doesn't exist */
192 #define BCM2835_MBOX_POWER_STATE_RESP_NODEV (1 << 1)
194 #define BCM2835_MBOX_TAG_GET_POWER_STATE 0x00020001
196 struct bcm2835_mbox_tag_get_power_state {
197 struct bcm2835_mbox_tag_hdr tag_hdr;
209 #define BCM2835_MBOX_TAG_SET_POWER_STATE 0x00028001
211 #define BCM2835_MBOX_SET_POWER_STATE_REQ_ON (1 << 0)
212 #define BCM2835_MBOX_SET_POWER_STATE_REQ_WAIT (1 << 1)
214 struct bcm2835_mbox_tag_set_power_state {
215 struct bcm2835_mbox_tag_hdr tag_hdr;
228 #define BCM2835_MBOX_TAG_GET_CLOCK_RATE 0x00030002
230 #define BCM2835_MBOX_CLOCK_ID_EMMC 1
231 #define BCM2835_MBOX_CLOCK_ID_UART 2
232 #define BCM2835_MBOX_CLOCK_ID_ARM 3
233 #define BCM2835_MBOX_CLOCK_ID_CORE 4
234 #define BCM2835_MBOX_CLOCK_ID_V3D 5
235 #define BCM2835_MBOX_CLOCK_ID_H264 6
236 #define BCM2835_MBOX_CLOCK_ID_ISP 7
237 #define BCM2835_MBOX_CLOCK_ID_SDRAM 8
238 #define BCM2835_MBOX_CLOCK_ID_PIXEL 9
239 #define BCM2835_MBOX_CLOCK_ID_PWM 10
241 struct bcm2835_mbox_tag_get_clock_rate {
242 struct bcm2835_mbox_tag_hdr tag_hdr;
254 #define BCM2835_MBOX_TAG_ALLOCATE_BUFFER 0x00040001
256 struct bcm2835_mbox_tag_allocate_buffer {
257 struct bcm2835_mbox_tag_hdr tag_hdr;
269 #define BCM2835_MBOX_TAG_RELEASE_BUFFER 0x00048001
271 struct bcm2835_mbox_tag_release_buffer {
272 struct bcm2835_mbox_tag_hdr tag_hdr;
281 #define BCM2835_MBOX_TAG_BLANK_SCREEN 0x00040002
283 struct bcm2835_mbox_tag_blank_screen {
284 struct bcm2835_mbox_tag_hdr tag_hdr;
287 /* bit 0 means on, other bots reserved */
296 /* Physical means output signal */
297 #define BCM2835_MBOX_TAG_GET_PHYSICAL_W_H 0x00040003
298 #define BCM2835_MBOX_TAG_TEST_PHYSICAL_W_H 0x00044003
299 #define BCM2835_MBOX_TAG_SET_PHYSICAL_W_H 0x00048003
301 struct bcm2835_mbox_tag_physical_w_h {
302 struct bcm2835_mbox_tag_hdr tag_hdr;
304 /* req not used for get */
316 /* Virtual means display buffer */
317 #define BCM2835_MBOX_TAG_GET_VIRTUAL_W_H 0x00040004
318 #define BCM2835_MBOX_TAG_TEST_VIRTUAL_W_H 0x00044004
319 #define BCM2835_MBOX_TAG_SET_VIRTUAL_W_H 0x00048004
321 struct bcm2835_mbox_tag_virtual_w_h {
322 struct bcm2835_mbox_tag_hdr tag_hdr;
324 /* req not used for get */
336 #define BCM2835_MBOX_TAG_GET_DEPTH 0x00040005
337 #define BCM2835_MBOX_TAG_TEST_DEPTH 0x00044005
338 #define BCM2835_MBOX_TAG_SET_DEPTH 0x00048005
340 struct bcm2835_mbox_tag_depth {
341 struct bcm2835_mbox_tag_hdr tag_hdr;
343 /* req not used for get */
353 #define BCM2835_MBOX_TAG_GET_PIXEL_ORDER 0x00040006
354 #define BCM2835_MBOX_TAG_TEST_PIXEL_ORDER 0x00044006
355 #define BCM2835_MBOX_TAG_SET_PIXEL_ORDER 0x00048006
357 #define BCM2835_MBOX_PIXEL_ORDER_BGR 0
358 #define BCM2835_MBOX_PIXEL_ORDER_RGB 1
360 struct bcm2835_mbox_tag_pixel_order {
361 struct bcm2835_mbox_tag_hdr tag_hdr;
363 /* req not used for get */
373 #define BCM2835_MBOX_TAG_GET_ALPHA_MODE 0x00040007
374 #define BCM2835_MBOX_TAG_TEST_ALPHA_MODE 0x00044007
375 #define BCM2835_MBOX_TAG_SET_ALPHA_MODE 0x00048007
377 #define BCM2835_MBOX_ALPHA_MODE_0_OPAQUE 0
378 #define BCM2835_MBOX_ALPHA_MODE_0_TRANSPARENT 1
379 #define BCM2835_MBOX_ALPHA_MODE_IGNORED 2
381 struct bcm2835_mbox_tag_alpha_mode {
382 struct bcm2835_mbox_tag_hdr tag_hdr;
384 /* req not used for get */
394 #define BCM2835_MBOX_TAG_GET_PITCH 0x00040008
396 struct bcm2835_mbox_tag_pitch {
397 struct bcm2835_mbox_tag_hdr tag_hdr;
407 /* Offset of display window within buffer */
408 #define BCM2835_MBOX_TAG_GET_VIRTUAL_OFFSET 0x00040009
409 #define BCM2835_MBOX_TAG_TEST_VIRTUAL_OFFSET 0x00044009
410 #define BCM2835_MBOX_TAG_SET_VIRTUAL_OFFSET 0x00048009
412 struct bcm2835_mbox_tag_virtual_offset {
413 struct bcm2835_mbox_tag_hdr tag_hdr;
415 /* req not used for get */
427 #define BCM2835_MBOX_TAG_GET_OVERSCAN 0x0004000a
428 #define BCM2835_MBOX_TAG_TEST_OVERSCAN 0x0004400a
429 #define BCM2835_MBOX_TAG_SET_OVERSCAN 0x0004800a
431 struct bcm2835_mbox_tag_overscan {
432 struct bcm2835_mbox_tag_hdr tag_hdr;
434 /* req not used for get */
450 #define BCM2835_MBOX_TAG_GET_PALETTE 0x0004000b
452 struct bcm2835_mbox_tag_get_palette {
453 struct bcm2835_mbox_tag_hdr tag_hdr;
463 #define BCM2835_MBOX_TAG_TEST_PALETTE 0x0004400b
465 struct bcm2835_mbox_tag_test_palette {
466 struct bcm2835_mbox_tag_hdr tag_hdr;
479 #define BCM2835_MBOX_TAG_SET_PALETTE 0x0004800b
481 struct bcm2835_mbox_tag_set_palette {
482 struct bcm2835_mbox_tag_hdr tag_hdr;
496 * Pass a raw u32 message to the VC, and receive a raw u32 back.
498 * Returns 0 for success, any other value for error.
500 int bcm2835_mbox_call_raw(u32 chan, u32 send, u32 *recv);
503 * Pass a complete property-style buffer to the VC, and wait until it has
506 * This function expects a pointer to the mbox_hdr structure in an attempt
507 * to ensure some degree of type safety. However, some number of tags and
508 * a termination value are expected to immediately follow the header in
509 * memory, as required by the property protocol.
511 * Each struct bcm2835_mbox_hdr passed must be allocated with
512 * ALLOC_CACHE_ALIGN_BUFFER(x, y, z) to ensure proper cache flush/invalidate.
514 * Returns 0 for success, any other value for error.
516 int bcm2835_mbox_call_prop(u32 chan, struct bcm2835_mbox_hdr *buffer);