1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * (C) Copyright 2012,2015 Stephen Warren
6 #ifndef _BCM2835_MBOX_H
7 #define _BCM2835_MBOX_H
9 #include <linux/compiler.h>
12 * The BCM2835 SoC contains (at least) two CPUs; the VideoCore (a/k/a "GPU")
13 * and the ARM CPU. The ARM CPU is often thought of as the main CPU.
14 * However, the VideoCore actually controls the initial SoC boot, and hides
15 * much of the hardware behind a protocol. This protocol is transported
16 * using the SoC's mailbox hardware module.
18 * The mailbox hardware supports passing 32-bit values back and forth.
19 * Presumably by software convention of the firmware, the bottom 4 bits of the
20 * value are used to indicate a logical channel, and the upper 28 bits are the
21 * actual payload. Various channels exist using these simple raw messages. See
22 * https://github.com/raspberrypi/firmware/wiki/Mailboxes for a list. As an
23 * example, the messages on the power management channel are a bitmask of
24 * devices whose power should be enabled.
26 * The property mailbox channel passes messages that contain the (16-byte
27 * aligned) ARM physical address of a memory buffer. This buffer is passed to
28 * the VC for processing, is modified in-place by the VC, and the address then
29 * passed back to the ARM CPU as the response mailbox message to indicate
30 * request completion. The buffers have a generic and extensible format; each
31 * buffer contains a standard header, a list of "tags", and a terminating zero
32 * entry. Each tag contains an ID indicating its type, and length fields for
33 * generic parsing. With some limitations, an arbitrary set of tags may be
34 * combined together into a single message buffer. This file defines structs
35 * representing the header and many individual tag layouts and IDs.
40 #define BCM2835_MBOX_PHYSADDR (CONFIG_BCM283x_BASE + 0x0000b880)
42 struct bcm2835_mbox_regs {
53 #define BCM2835_MBOX_STATUS_WR_FULL 0x80000000
54 #define BCM2835_MBOX_STATUS_RD_EMPTY 0x40000000
56 /* Lower 4-bits are channel ID */
57 #define BCM2835_CHAN_MASK 0xf
58 #define BCM2835_MBOX_PACK(chan, data) (((data) & (~BCM2835_CHAN_MASK)) | \
59 (chan & BCM2835_CHAN_MASK))
60 #define BCM2835_MBOX_UNPACK_CHAN(val) ((val) & BCM2835_CHAN_MASK)
61 #define BCM2835_MBOX_UNPACK_DATA(val) ((val) & (~BCM2835_CHAN_MASK))
63 /* Property mailbox buffer structures */
65 #define BCM2835_MBOX_PROP_CHAN 8
67 /* All message buffers must start with this header */
68 struct bcm2835_mbox_hdr {
73 #define BCM2835_MBOX_REQ_CODE 0
74 #define BCM2835_MBOX_RESP_CODE_SUCCESS 0x80000000
76 #define BCM2835_MBOX_INIT_HDR(_m_) { \
77 memset((_m_), 0, sizeof(*(_m_))); \
78 (_m_)->hdr.buf_size = sizeof(*(_m_)); \
79 (_m_)->hdr.code = 0; \
84 * A message buffer contains a list of tags. Each tag must also start with
85 * a standardized header.
87 struct bcm2835_mbox_tag_hdr {
93 #define BCM2835_MBOX_INIT_TAG(_t_, _id_) { \
94 (_t_)->tag_hdr.tag = BCM2835_MBOX_TAG_##_id_; \
95 (_t_)->tag_hdr.val_buf_size = sizeof((_t_)->body); \
96 (_t_)->tag_hdr.val_len = sizeof((_t_)->body.req); \
99 #define BCM2835_MBOX_INIT_TAG_NO_REQ(_t_, _id_) { \
100 (_t_)->tag_hdr.tag = BCM2835_MBOX_TAG_##_id_; \
101 (_t_)->tag_hdr.val_buf_size = sizeof((_t_)->body); \
102 (_t_)->tag_hdr.val_len = 0; \
105 /* When responding, the VC sets this bit in val_len to indicate a response */
106 #define BCM2835_MBOX_TAG_VAL_LEN_RESPONSE 0x80000000
109 * Below we define the ID and struct for many possible tags. This header only
110 * defines individual tag structs, not entire message structs, since in
111 * general an arbitrary set of tags may be combined into a single message.
112 * Clients of the mbox API are expected to define their own overall message
113 * structures by combining the header, a set of tags, and a terminating
114 * entry. For example,
117 * struct bcm2835_mbox_hdr hdr;
118 * struct bcm2835_mbox_tag_get_arm_mem get_arm_mem;
119 * ... perhaps other tags here ...
124 #define BCM2835_MBOX_TAG_GET_BOARD_REV 0x00010002
126 struct bcm2835_mbox_tag_get_board_rev {
127 struct bcm2835_mbox_tag_hdr tag_hdr;
137 #define BCM2835_MBOX_TAG_GET_MAC_ADDRESS 0x00010003
139 struct bcm2835_mbox_tag_get_mac_address {
140 struct bcm2835_mbox_tag_hdr tag_hdr;
151 #define BCM2835_MBOX_TAG_GET_BOARD_SERIAL 0x00010004
153 struct bcm2835_mbox_tag_get_board_serial {
154 struct bcm2835_mbox_tag_hdr tag_hdr;
162 #define BCM2835_MBOX_TAG_GET_ARM_MEMORY 0x00010005
164 struct bcm2835_mbox_tag_get_arm_mem {
165 struct bcm2835_mbox_tag_hdr tag_hdr;
176 #define BCM2835_MBOX_POWER_DEVID_SDHCI 0
177 #define BCM2835_MBOX_POWER_DEVID_UART0 1
178 #define BCM2835_MBOX_POWER_DEVID_UART1 2
179 #define BCM2835_MBOX_POWER_DEVID_USB_HCD 3
180 #define BCM2835_MBOX_POWER_DEVID_I2C0 4
181 #define BCM2835_MBOX_POWER_DEVID_I2C1 5
182 #define BCM2835_MBOX_POWER_DEVID_I2C2 6
183 #define BCM2835_MBOX_POWER_DEVID_SPI 7
184 #define BCM2835_MBOX_POWER_DEVID_CCP2TX 8
186 #define BCM2835_MBOX_POWER_STATE_RESP_ON (1 << 0)
187 /* Device doesn't exist */
188 #define BCM2835_MBOX_POWER_STATE_RESP_NODEV (1 << 1)
190 #define BCM2835_MBOX_TAG_GET_POWER_STATE 0x00020001
192 struct bcm2835_mbox_tag_get_power_state {
193 struct bcm2835_mbox_tag_hdr tag_hdr;
205 #define BCM2835_MBOX_TAG_SET_POWER_STATE 0x00028001
207 #define BCM2835_MBOX_SET_POWER_STATE_REQ_ON (1 << 0)
208 #define BCM2835_MBOX_SET_POWER_STATE_REQ_WAIT (1 << 1)
210 struct bcm2835_mbox_tag_set_power_state {
211 struct bcm2835_mbox_tag_hdr tag_hdr;
224 #define BCM2835_MBOX_TAG_GET_CLOCK_RATE 0x00030002
226 #define BCM2835_MBOX_CLOCK_ID_EMMC 1
227 #define BCM2835_MBOX_CLOCK_ID_UART 2
228 #define BCM2835_MBOX_CLOCK_ID_ARM 3
229 #define BCM2835_MBOX_CLOCK_ID_CORE 4
230 #define BCM2835_MBOX_CLOCK_ID_V3D 5
231 #define BCM2835_MBOX_CLOCK_ID_H264 6
232 #define BCM2835_MBOX_CLOCK_ID_ISP 7
233 #define BCM2835_MBOX_CLOCK_ID_SDRAM 8
234 #define BCM2835_MBOX_CLOCK_ID_PIXEL 9
235 #define BCM2835_MBOX_CLOCK_ID_PWM 10
237 struct bcm2835_mbox_tag_get_clock_rate {
238 struct bcm2835_mbox_tag_hdr tag_hdr;
250 #define BCM2835_MBOX_TAG_ALLOCATE_BUFFER 0x00040001
252 struct bcm2835_mbox_tag_allocate_buffer {
253 struct bcm2835_mbox_tag_hdr tag_hdr;
265 #define BCM2835_MBOX_TAG_RELEASE_BUFFER 0x00048001
267 struct bcm2835_mbox_tag_release_buffer {
268 struct bcm2835_mbox_tag_hdr tag_hdr;
277 #define BCM2835_MBOX_TAG_BLANK_SCREEN 0x00040002
279 struct bcm2835_mbox_tag_blank_screen {
280 struct bcm2835_mbox_tag_hdr tag_hdr;
283 /* bit 0 means on, other bots reserved */
292 /* Physical means output signal */
293 #define BCM2835_MBOX_TAG_GET_PHYSICAL_W_H 0x00040003
294 #define BCM2835_MBOX_TAG_TEST_PHYSICAL_W_H 0x00044003
295 #define BCM2835_MBOX_TAG_SET_PHYSICAL_W_H 0x00048003
297 struct bcm2835_mbox_tag_physical_w_h {
298 struct bcm2835_mbox_tag_hdr tag_hdr;
300 /* req not used for get */
312 /* Virtual means display buffer */
313 #define BCM2835_MBOX_TAG_GET_VIRTUAL_W_H 0x00040004
314 #define BCM2835_MBOX_TAG_TEST_VIRTUAL_W_H 0x00044004
315 #define BCM2835_MBOX_TAG_SET_VIRTUAL_W_H 0x00048004
317 struct bcm2835_mbox_tag_virtual_w_h {
318 struct bcm2835_mbox_tag_hdr tag_hdr;
320 /* req not used for get */
332 #define BCM2835_MBOX_TAG_GET_DEPTH 0x00040005
333 #define BCM2835_MBOX_TAG_TEST_DEPTH 0x00044005
334 #define BCM2835_MBOX_TAG_SET_DEPTH 0x00048005
336 struct bcm2835_mbox_tag_depth {
337 struct bcm2835_mbox_tag_hdr tag_hdr;
339 /* req not used for get */
349 #define BCM2835_MBOX_TAG_GET_PIXEL_ORDER 0x00040006
350 #define BCM2835_MBOX_TAG_TEST_PIXEL_ORDER 0x00044006
351 #define BCM2835_MBOX_TAG_SET_PIXEL_ORDER 0x00048006
353 #define BCM2835_MBOX_PIXEL_ORDER_BGR 0
354 #define BCM2835_MBOX_PIXEL_ORDER_RGB 1
356 struct bcm2835_mbox_tag_pixel_order {
357 struct bcm2835_mbox_tag_hdr tag_hdr;
359 /* req not used for get */
369 #define BCM2835_MBOX_TAG_GET_ALPHA_MODE 0x00040007
370 #define BCM2835_MBOX_TAG_TEST_ALPHA_MODE 0x00044007
371 #define BCM2835_MBOX_TAG_SET_ALPHA_MODE 0x00048007
373 #define BCM2835_MBOX_ALPHA_MODE_0_OPAQUE 0
374 #define BCM2835_MBOX_ALPHA_MODE_0_TRANSPARENT 1
375 #define BCM2835_MBOX_ALPHA_MODE_IGNORED 2
377 struct bcm2835_mbox_tag_alpha_mode {
378 struct bcm2835_mbox_tag_hdr tag_hdr;
380 /* req not used for get */
390 #define BCM2835_MBOX_TAG_GET_PITCH 0x00040008
392 struct bcm2835_mbox_tag_pitch {
393 struct bcm2835_mbox_tag_hdr tag_hdr;
403 /* Offset of display window within buffer */
404 #define BCM2835_MBOX_TAG_GET_VIRTUAL_OFFSET 0x00040009
405 #define BCM2835_MBOX_TAG_TEST_VIRTUAL_OFFSET 0x00044009
406 #define BCM2835_MBOX_TAG_SET_VIRTUAL_OFFSET 0x00048009
408 struct bcm2835_mbox_tag_virtual_offset {
409 struct bcm2835_mbox_tag_hdr tag_hdr;
411 /* req not used for get */
423 #define BCM2835_MBOX_TAG_GET_OVERSCAN 0x0004000a
424 #define BCM2835_MBOX_TAG_TEST_OVERSCAN 0x0004400a
425 #define BCM2835_MBOX_TAG_SET_OVERSCAN 0x0004800a
427 struct bcm2835_mbox_tag_overscan {
428 struct bcm2835_mbox_tag_hdr tag_hdr;
430 /* req not used for get */
446 #define BCM2835_MBOX_TAG_GET_PALETTE 0x0004000b
448 struct bcm2835_mbox_tag_get_palette {
449 struct bcm2835_mbox_tag_hdr tag_hdr;
459 #define BCM2835_MBOX_TAG_TEST_PALETTE 0x0004400b
461 struct bcm2835_mbox_tag_test_palette {
462 struct bcm2835_mbox_tag_hdr tag_hdr;
475 #define BCM2835_MBOX_TAG_SET_PALETTE 0x0004800b
477 struct bcm2835_mbox_tag_set_palette {
478 struct bcm2835_mbox_tag_hdr tag_hdr;
492 * Pass a raw u32 message to the VC, and receive a raw u32 back.
494 * Returns 0 for success, any other value for error.
496 int bcm2835_mbox_call_raw(u32 chan, u32 send, u32 *recv);
499 * Pass a complete property-style buffer to the VC, and wait until it has
502 * This function expects a pointer to the mbox_hdr structure in an attempt
503 * to ensure some degree of type safety. However, some number of tags and
504 * a termination value are expected to immediately follow the header in
505 * memory, as required by the property protocol.
507 * Each struct bcm2835_mbox_hdr passed must be allocated with
508 * ALLOC_CACHE_ALIGN_BUFFER(x, y, z) to ensure proper cache flush/invalidate.
510 * Returns 0 for success, any other value for error.
512 int bcm2835_mbox_call_prop(u32 chan, struct bcm2835_mbox_hdr *buffer);