1 // SPDX-License-Identifier: GPL-2.0+
3 * (C) Copyright 2014 DENX Software Engineering
4 * Heiko Schocher <hs@denx.de>
7 * Copyright (C) 2013 Atmel Corporation
8 * Bo Shen <voice.shen@atmel.com>
14 #include <asm/arch/at91_common.h>
15 #include <asm/arch/at91sam9_matrix.h>
16 #include <asm/arch/at91_pit.h>
17 #include <asm/arch/at91_rstc.h>
18 #include <asm/arch/at91_wdt.h>
19 #include <asm/arch/clk.h>
22 DECLARE_GLOBAL_DATA_PTR;
24 static void enable_ext_reset(void)
26 struct at91_rstc *rstc = (struct at91_rstc *)ATMEL_BASE_RSTC;
28 writel(AT91_RSTC_KEY | AT91_RSTC_MR_URSTEN, &rstc->mr);
31 void lowlevel_clock_init(void)
33 struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
35 if (!(readl(&pmc->sr) & AT91_PMC_MOSCS)) {
36 /* Enable Main Oscillator */
37 writel(AT91_PMC_MOSCS | (0x40 << 8), &pmc->mor);
39 /* Wait until Main Oscillator is stable */
40 while (!(readl(&pmc->sr) & AT91_PMC_MOSCS))
44 /* After stabilization, switch to Main Oscillator */
45 if ((readl(&pmc->mckr) & AT91_PMC_CSS) == AT91_PMC_CSS_SLOW) {
48 tmp = readl(&pmc->mckr);
50 tmp |= AT91_PMC_CSS_MAIN;
51 writel(tmp, &pmc->mckr);
52 while (!(readl(&pmc->sr) & AT91_PMC_MCKRDY))
55 tmp &= ~AT91_PMC_PRES;
56 tmp |= AT91_PMC_PRES_1;
57 writel(tmp, &pmc->mckr);
58 while (!(readl(&pmc->sr) & AT91_PMC_MCKRDY))
65 void __weak matrix_init(void)
69 void __weak at91_spl_board_init(void)
73 void __weak spl_board_init(void)
77 void board_init_f(ulong dummy)
79 #if CONFIG_IS_ENABLED(OF_CONTROL)
82 ret = spl_early_init();
84 debug("spl_early_init() failed: %d\n", ret);
89 lowlevel_clock_init();
90 #if !defined(CONFIG_WDT_AT91)
95 * At this stage the main oscillator is supposed to be enabled
98 at91_pllicpr_init(0x00);
100 /* Configure PLLA = MOSC * (PLL_MULA + 1) / PLL_DIVA */
101 at91_plla_init(CONFIG_SYS_AT91_PLLA);
103 /* PCK = PLLA = 2 * MCK */
104 at91_mck_init(CONFIG_SYS_MCKR);
106 /* Switch MCK on PLLA output */
107 at91_mck_init(CONFIG_SYS_MCKR_CSS);
109 #if defined(CONFIG_SYS_AT91_PLLB)
111 at91_pllb_init(CONFIG_SYS_AT91_PLLB);
114 /* Enable External Reset */
117 /* Initialize matrix */
120 gd->arch.mck_rate_hz = CONFIG_SYS_MASTER_CLOCK;
122 * init timer long enough for using in spl.
126 /* enable clocks for all PIOs */
127 #if defined(CONFIG_AT91SAM9X5) || defined(CONFIG_AT91SAM9N12)
128 at91_periph_clk_enable(ATMEL_ID_PIOAB);
129 at91_periph_clk_enable(ATMEL_ID_PIOCD);
131 at91_periph_clk_enable(ATMEL_ID_PIOA);
132 at91_periph_clk_enable(ATMEL_ID_PIOB);
133 at91_periph_clk_enable(ATMEL_ID_PIOC);
136 #if defined(CONFIG_SPL_SERIAL_SUPPORT)
138 at91_seriald_hw_init();
139 preloader_console_init();
144 at91_spl_board_init();