1 // SPDX-License-Identifier: GPL-2.0+
3 * (C) Copyright 2014 DENX Software Engineering
4 * Heiko Schocher <hs@denx.de>
7 * Copyright (C) 2013 Atmel Corporation
8 * Bo Shen <voice.shen@atmel.com>
13 #include <asm/arch/at91_common.h>
14 #include <asm/arch/at91sam9_matrix.h>
15 #include <asm/arch/at91_pit.h>
16 #include <asm/arch/at91_rstc.h>
17 #include <asm/arch/at91_wdt.h>
18 #include <asm/arch/clk.h>
21 DECLARE_GLOBAL_DATA_PTR;
23 static void enable_ext_reset(void)
25 struct at91_rstc *rstc = (struct at91_rstc *)ATMEL_BASE_RSTC;
27 writel(AT91_RSTC_KEY | AT91_RSTC_MR_URSTEN, &rstc->mr);
30 void lowlevel_clock_init(void)
32 struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
34 if (!(readl(&pmc->sr) & AT91_PMC_MOSCS)) {
35 /* Enable Main Oscillator */
36 writel(AT91_PMC_MOSCS | (0x40 << 8), &pmc->mor);
38 /* Wait until Main Oscillator is stable */
39 while (!(readl(&pmc->sr) & AT91_PMC_MOSCS))
43 /* After stabilization, switch to Main Oscillator */
44 if ((readl(&pmc->mckr) & AT91_PMC_CSS) == AT91_PMC_CSS_SLOW) {
47 tmp = readl(&pmc->mckr);
49 tmp |= AT91_PMC_CSS_MAIN;
50 writel(tmp, &pmc->mckr);
51 while (!(readl(&pmc->sr) & AT91_PMC_MCKRDY))
54 tmp &= ~AT91_PMC_PRES;
55 tmp |= AT91_PMC_PRES_1;
56 writel(tmp, &pmc->mckr);
57 while (!(readl(&pmc->sr) & AT91_PMC_MCKRDY))
64 void __weak matrix_init(void)
68 void __weak at91_spl_board_init(void)
72 void __weak spl_board_init(void)
76 void board_init_f(ulong dummy)
78 #if CONFIG_IS_ENABLED(OF_CONTROL)
81 ret = spl_early_init();
83 debug("spl_early_init() failed: %d\n", ret);
88 lowlevel_clock_init();
89 #if !defined(CONFIG_WDT_AT91)
94 * At this stage the main oscillator is supposed to be enabled
97 at91_pllicpr_init(0x00);
99 /* Configure PLLA = MOSC * (PLL_MULA + 1) / PLL_DIVA */
100 at91_plla_init(CONFIG_SYS_AT91_PLLA);
102 /* PCK = PLLA = 2 * MCK */
103 at91_mck_init(CONFIG_SYS_MCKR);
105 /* Switch MCK on PLLA output */
106 at91_mck_init(CONFIG_SYS_MCKR_CSS);
108 #if defined(CONFIG_SYS_AT91_PLLB)
110 at91_pllb_init(CONFIG_SYS_AT91_PLLB);
113 /* Enable External Reset */
116 /* Initialize matrix */
119 gd->arch.mck_rate_hz = CONFIG_SYS_MASTER_CLOCK;
121 * init timer long enough for using in spl.
125 /* enable clocks for all PIOs */
126 #if defined(CONFIG_AT91SAM9X5) || defined(CONFIG_AT91SAM9N12)
127 at91_periph_clk_enable(ATMEL_ID_PIOAB);
128 at91_periph_clk_enable(ATMEL_ID_PIOCD);
130 at91_periph_clk_enable(ATMEL_ID_PIOA);
131 at91_periph_clk_enable(ATMEL_ID_PIOB);
132 at91_periph_clk_enable(ATMEL_ID_PIOC);
135 #if defined(CONFIG_SPL_SERIAL_SUPPORT)
137 at91_seriald_hw_init();
138 preloader_console_init();
143 at91_spl_board_init();