1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2013 Atmel Corporation
4 * Bo Shen <voice.shen@atmel.com>
6 * Copyright (C) 2015 Atmel Corporation
7 * Wenyou Yang <wenyou.yang@atmel.com>
12 #include <asm/arch/atmel_mpddrc.h>
14 #define SAMA5D3_MPDDRC_VERSION 0x140
16 static inline void atmel_mpddr_op(const struct atmel_mpddr *mpddr,
20 writel(mode, &mpddr->mr);
21 writel(0, ram_address);
24 static int ddr2_decodtype_is_seq(const unsigned int base, u32 cr)
26 struct atmel_mpddr *mpddr = (struct atmel_mpddr *)base;
27 u16 version = readl(&mpddr->version) & 0xffff;
29 if ((version >= SAMA5D3_MPDDRC_VERSION) &&
30 (cr & ATMEL_MPDDRC_CR_DECOD_INTERLEAVED))
37 int ddr2_init(const unsigned int base,
38 const unsigned int ram_address,
39 const struct atmel_mpddrc_config *mpddr_value)
41 const struct atmel_mpddr *mpddr = (struct atmel_mpddr *)base;
45 /* Compute bank offset according to NC in configuration register */
46 ba_off = (mpddr_value->cr & ATMEL_MPDDRC_CR_NC_MASK) + 9;
47 if (ddr2_decodtype_is_seq(base, mpddr_value->cr))
48 ba_off += ((mpddr_value->cr & ATMEL_MPDDRC_CR_NR_MASK) >> 2) + 11;
50 ba_off += (mpddr_value->md & ATMEL_MPDDRC_MD_DBW_MASK) ? 1 : 2;
52 /* Program the memory device type into the memory device register */
53 writel(mpddr_value->md, &mpddr->md);
55 /* Program the configuration register */
56 writel(mpddr_value->cr, &mpddr->cr);
58 /* Program the timing register */
59 writel(mpddr_value->tpr0, &mpddr->tpr0);
60 writel(mpddr_value->tpr1, &mpddr->tpr1);
61 writel(mpddr_value->tpr2, &mpddr->tpr2);
63 /* Issue a NOP command */
64 atmel_mpddr_op(mpddr, ATMEL_MPDDRC_MR_MODE_NOP_CMD, ram_address);
66 /* A 200 us is provided to precede any signal toggle */
69 /* Issue a NOP command */
70 atmel_mpddr_op(mpddr, ATMEL_MPDDRC_MR_MODE_NOP_CMD, ram_address);
72 /* Issue an all banks precharge command */
73 atmel_mpddr_op(mpddr, ATMEL_MPDDRC_MR_MODE_PRCGALL_CMD, ram_address);
75 /* Issue an extended mode register set(EMRS2) to choose operation */
76 atmel_mpddr_op(mpddr, ATMEL_MPDDRC_MR_MODE_EXT_LMR_CMD,
77 ram_address + (0x2 << ba_off));
79 /* Issue an extended mode register set(EMRS3) to set EMSR to 0 */
80 atmel_mpddr_op(mpddr, ATMEL_MPDDRC_MR_MODE_EXT_LMR_CMD,
81 ram_address + (0x3 << ba_off));
84 * Issue an extended mode register set(EMRS1) to enable DLL and
85 * program D.I.C (output driver impedance control)
87 atmel_mpddr_op(mpddr, ATMEL_MPDDRC_MR_MODE_EXT_LMR_CMD,
88 ram_address + (0x1 << ba_off));
90 /* Enable DLL reset */
91 cr = readl(&mpddr->cr);
92 writel(cr | ATMEL_MPDDRC_CR_DLL_RESET_ENABLED, &mpddr->cr);
94 /* A mode register set(MRS) cycle is issued to reset DLL */
95 atmel_mpddr_op(mpddr, ATMEL_MPDDRC_MR_MODE_LMR_CMD, ram_address);
97 /* Issue an all banks precharge command */
98 atmel_mpddr_op(mpddr, ATMEL_MPDDRC_MR_MODE_PRCGALL_CMD, ram_address);
100 /* Two auto-refresh (CBR) cycles are provided */
101 atmel_mpddr_op(mpddr, ATMEL_MPDDRC_MR_MODE_RFSH_CMD, ram_address);
102 atmel_mpddr_op(mpddr, ATMEL_MPDDRC_MR_MODE_RFSH_CMD, ram_address);
104 /* Disable DLL reset */
105 cr = readl(&mpddr->cr);
106 writel(cr & (~ATMEL_MPDDRC_CR_DLL_RESET_ENABLED), &mpddr->cr);
108 /* A mode register set (MRS) cycle is issued to disable DLL reset */
109 atmel_mpddr_op(mpddr, ATMEL_MPDDRC_MR_MODE_LMR_CMD, ram_address);
111 /* Set OCD calibration in default state */
112 cr = readl(&mpddr->cr);
113 writel(cr | ATMEL_MPDDRC_CR_OCD_DEFAULT, &mpddr->cr);
116 * An extended mode register set (EMRS1) cycle is issued
117 * to OCD default value
119 atmel_mpddr_op(mpddr, ATMEL_MPDDRC_MR_MODE_EXT_LMR_CMD,
120 ram_address + (0x1 << ba_off));
122 /* OCD calibration mode exit */
123 cr = readl(&mpddr->cr);
124 writel(cr & (~ATMEL_MPDDRC_CR_OCD_DEFAULT), &mpddr->cr);
127 * An extended mode register set (EMRS1) cycle is issued
130 atmel_mpddr_op(mpddr, ATMEL_MPDDRC_MR_MODE_EXT_LMR_CMD,
131 ram_address + (0x1 << ba_off));
133 /* A nornal mode command is provided */
134 atmel_mpddr_op(mpddr, ATMEL_MPDDRC_MR_MODE_NORMAL_CMD, ram_address);
136 /* Perform a write access to any DDR2-SDRAM address */
137 writel(0, ram_address);
139 /* Write the refresh rate */
140 writel(mpddr_value->rtr, &mpddr->rtr);
145 int ddr3_init(const unsigned int base,
146 const unsigned int ram_address,
147 const struct atmel_mpddrc_config *mpddr_value)
149 struct atmel_mpddr *mpddr = (struct atmel_mpddr *)base;
152 /* Compute bank offset according to NC in configuration register */
153 ba_off = (mpddr_value->cr & ATMEL_MPDDRC_CR_NC_MASK) + 9;
154 if (ddr2_decodtype_is_seq(base, mpddr_value->cr))
155 ba_off += ((mpddr_value->cr &
156 ATMEL_MPDDRC_CR_NR_MASK) >> 2) + 11;
158 ba_off += (mpddr_value->md & ATMEL_MPDDRC_MD_DBW_MASK) ? 1 : 2;
160 /* Program the memory device type */
161 writel(mpddr_value->md, &mpddr->md);
164 * Program features of the DDR3-SDRAM device and timing parameters
166 writel(mpddr_value->cr, &mpddr->cr);
168 writel(mpddr_value->tpr0, &mpddr->tpr0);
169 writel(mpddr_value->tpr1, &mpddr->tpr1);
170 writel(mpddr_value->tpr2, &mpddr->tpr2);
172 /* A NOP command is issued to the DDR3-SRAM */
173 atmel_mpddr_op(mpddr, ATMEL_MPDDRC_MR_MODE_NOP_CMD, ram_address);
175 /* A pause of at least 500us must be observed before a single toggle. */
178 /* A NOP command is issued to the DDR3-SDRAM */
179 atmel_mpddr_op(mpddr, ATMEL_MPDDRC_MR_MODE_NOP_CMD, ram_address);
182 * An Extended Mode Register Set (EMRS2) cycle is issued to choose
183 * between commercial or high temperature operations.
185 atmel_mpddr_op(mpddr, ATMEL_MPDDRC_MR_MODE_EXT_LMR_CMD,
186 ram_address + (0x2 << ba_off));
188 * Step 7: An Extended Mode Register Set (EMRS3) cycle is issued to set
189 * the Extended Mode Register to 0.
191 atmel_mpddr_op(mpddr, ATMEL_MPDDRC_MR_MODE_EXT_LMR_CMD,
192 ram_address + (0x3 << ba_off));
194 * An Extended Mode Register Set (EMRS1) cycle is issued to disable and
195 * to program O.D.S. (Output Driver Strength).
197 atmel_mpddr_op(mpddr, ATMEL_MPDDRC_MR_MODE_EXT_LMR_CMD,
198 ram_address + (0x1 << ba_off));
201 * Write a one to the DLL bit (enable DLL reset) in the MPDDRC
202 * Configuration Register.
205 /* A Mode Register Set (MRS) cycle is issued to reset DLL. */
206 atmel_mpddr_op(mpddr, ATMEL_MPDDRC_MR_MODE_LMR_CMD, ram_address);
211 * A Calibration command (MRS) is issued to calibrate RTT and RON
212 * values for the Process Voltage Temperature (PVT).
214 atmel_mpddr_op(mpddr, ATMEL_MPDDRC_MR_MODE_DEEP_CMD, ram_address);
216 /* A Normal Mode command is provided. */
217 atmel_mpddr_op(mpddr, ATMEL_MPDDRC_MR_MODE_NORMAL_CMD, ram_address);
219 /* Perform a write access to any DDR3-SDRAM address. */
220 writel(0, ram_address);
223 * Write the refresh rate into the COUNT field in the MPDDRC
224 * Refresh Timer Register (MPDDRC_RTR):
226 writel(mpddr_value->rtr, &mpddr->rtr);