3 * Stelian Pop <stelian@popies.net>
4 * Lead Tech Design <www.leadtechdesign.com>
5 * Copyright (C) 2009 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
7 * SPDX-License-Identifier: GPL-2.0+
9 #ifndef __ASM_ARM_ARCH_CLK_H__
10 #define __ASM_ARM_ARCH_CLK_H__
12 #include <asm/arch/hardware.h>
13 #include <asm/arch/at91_pmc.h>
14 #include <asm/global_data.h>
16 #define GCK_CSS_SLOW_CLK 0
17 #define GCK_CSS_MAIN_CLK 1
18 #define GCK_CSS_PLLA_CLK 2
19 #define GCK_CSS_UPLL_CLK 3
20 #define GCK_CSS_MCK_CLK 4
21 #define GCK_CSS_AUDIO_CLK 5
23 #define AT91_UTMI_PLL_CLK_FREQ 480000000
25 static inline unsigned long get_cpu_clk_rate(void)
27 DECLARE_GLOBAL_DATA_PTR;
28 return gd->arch.cpu_clk_rate_hz;
31 static inline unsigned long get_main_clk_rate(void)
33 DECLARE_GLOBAL_DATA_PTR;
34 return gd->arch.main_clk_rate_hz;
37 static inline unsigned long get_mck_clk_rate(void)
39 DECLARE_GLOBAL_DATA_PTR;
40 return gd->arch.mck_rate_hz;
43 static inline unsigned long get_plla_clk_rate(void)
45 DECLARE_GLOBAL_DATA_PTR;
46 return gd->arch.plla_rate_hz;
49 static inline unsigned long get_pllb_clk_rate(void)
51 DECLARE_GLOBAL_DATA_PTR;
52 return gd->arch.pllb_rate_hz;
55 static inline u32 get_pllb_init(void)
57 DECLARE_GLOBAL_DATA_PTR;
58 return gd->arch.at91_pllb_usb_init;
61 #ifdef CPU_HAS_H32MXDIV
62 static inline unsigned int get_h32mxdiv(void)
64 struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
66 return readl(&pmc->mckr) & AT91_PMC_MCKR_H32MXDIV;
69 static inline unsigned int get_h32mxdiv(void)
75 static inline unsigned long get_macb_pclk_rate(unsigned int dev_id)
78 return get_mck_clk_rate() / 2;
80 return get_mck_clk_rate();
83 static inline unsigned long get_usart_clk_rate(unsigned int dev_id)
86 return get_mck_clk_rate() / 2;
88 return get_mck_clk_rate();
91 static inline unsigned long get_lcdc_clk_rate(unsigned int dev_id)
93 return get_mck_clk_rate();
96 static inline unsigned long get_spi_clk_rate(unsigned int dev_id)
99 return get_mck_clk_rate() / 2;
101 return get_mck_clk_rate();
104 static inline unsigned long get_twi_clk_rate(unsigned int dev_id)
107 return get_mck_clk_rate() / 2;
109 return get_mck_clk_rate();
112 static inline unsigned long get_mci_clk_rate(void)
115 return get_mck_clk_rate() / 2;
117 return get_mck_clk_rate();
120 static inline unsigned long get_pit_clk_rate(void)
123 return get_mck_clk_rate() / 2;
125 return get_mck_clk_rate();
128 int at91_clock_init(unsigned long main_clock);
129 void at91_periph_clk_enable(int id);
130 void at91_periph_clk_disable(int id);
131 int at91_enable_periph_generated_clk(u32 id, u32 clk_source, u32 div);
132 u32 at91_get_periph_generated_clk(u32 id);
133 void at91_system_clk_enable(int sys_clk);
134 void at91_system_clk_disable(int sys_clk);
135 int at91_upll_clk_enable(void);
136 int at91_upll_clk_disable(void);
137 void at91_usb_clk_init(u32 value);
138 int at91_pllb_clk_enable(u32 pllbr);
139 int at91_pllb_clk_disable(void);
140 void at91_pllicpr_init(u32 icpr);
142 #endif /* __ASM_ARM_ARCH_CLK_H__ */