3 * Stelian Pop <stelian@popies.net>
4 * Lead Tech Design <www.leadtechdesign.com>
5 * Copyright (C) 2009 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
7 * SPDX-License-Identifier: GPL-2.0+
9 #ifndef __ASM_ARM_ARCH_CLK_H__
10 #define __ASM_ARM_ARCH_CLK_H__
12 #include <asm/arch/hardware.h>
13 #include <asm/arch/at91_pmc.h>
14 #include <asm/global_data.h>
16 #define GCK_CSS_SLOW_CLK 0
17 #define GCK_CSS_MAIN_CLK 1
18 #define GCK_CSS_PLLA_CLK 2
19 #define GCK_CSS_UPLL_CLK 3
20 #define GCK_CSS_MCK_CLK 4
21 #define GCK_CSS_AUDIO_CLK 5
23 static inline unsigned long get_cpu_clk_rate(void)
25 DECLARE_GLOBAL_DATA_PTR;
26 return gd->arch.cpu_clk_rate_hz;
29 static inline unsigned long get_main_clk_rate(void)
31 DECLARE_GLOBAL_DATA_PTR;
32 return gd->arch.main_clk_rate_hz;
35 static inline unsigned long get_mck_clk_rate(void)
37 DECLARE_GLOBAL_DATA_PTR;
38 return gd->arch.mck_rate_hz;
41 static inline unsigned long get_plla_clk_rate(void)
43 DECLARE_GLOBAL_DATA_PTR;
44 return gd->arch.plla_rate_hz;
47 static inline unsigned long get_pllb_clk_rate(void)
49 DECLARE_GLOBAL_DATA_PTR;
50 return gd->arch.pllb_rate_hz;
53 static inline u32 get_pllb_init(void)
55 DECLARE_GLOBAL_DATA_PTR;
56 return gd->arch.at91_pllb_usb_init;
59 #ifdef CPU_HAS_H32MXDIV
60 static inline unsigned int get_h32mxdiv(void)
62 struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
64 return readl(&pmc->mckr) & AT91_PMC_MCKR_H32MXDIV;
67 static inline unsigned int get_h32mxdiv(void)
73 static inline unsigned long get_macb_pclk_rate(unsigned int dev_id)
76 return get_mck_clk_rate() / 2;
78 return get_mck_clk_rate();
81 static inline unsigned long get_usart_clk_rate(unsigned int dev_id)
84 return get_mck_clk_rate() / 2;
86 return get_mck_clk_rate();
89 static inline unsigned long get_lcdc_clk_rate(unsigned int dev_id)
91 return get_mck_clk_rate();
94 static inline unsigned long get_spi_clk_rate(unsigned int dev_id)
97 return get_mck_clk_rate() / 2;
99 return get_mck_clk_rate();
102 static inline unsigned long get_twi_clk_rate(unsigned int dev_id)
105 return get_mck_clk_rate() / 2;
107 return get_mck_clk_rate();
110 static inline unsigned long get_mci_clk_rate(void)
113 return get_mck_clk_rate() / 2;
115 return get_mck_clk_rate();
118 static inline unsigned long get_pit_clk_rate(void)
121 return get_mck_clk_rate() / 2;
123 return get_mck_clk_rate();
126 int at91_clock_init(unsigned long main_clock);
127 void at91_periph_clk_enable(int id);
128 void at91_periph_clk_disable(int id);
129 int at91_enable_periph_generated_clk(u32 id, u32 clk_source, u32 div);
130 u32 at91_get_periph_generated_clk(u32 id);
131 void at91_system_clk_enable(int sys_clk);
132 void at91_system_clk_disable(int sys_clk);
134 #endif /* __ASM_ARM_ARCH_CLK_H__ */