1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Matrix-centric header file for the AT91SAM9X5 family
5 * Copyright (C) 2012-2013 Atmel Corporation.
7 * Memory Controllers (MATRIX, EBI) - System peripherals registers.
8 * Based on AT91SAM9X5 & AT91SAM9N12 preliminary datasheet.
11 #ifndef __AT91SAM9X5_MATRIX_H__
12 #define __AT91SAM9X5_MATRIX_H__
16 /* AT91SAM9N12 Matrix definition is a subset of AT91SAM9X5. */
21 u32 mrcr; /* 0x100 Master Remap Control */
23 #ifdef CONFIG_AT91SAM9X5
26 /* EBI Chip Select Assignment Register
32 #ifdef CONFIG_AT91SAM9N12
39 #endif /* __ASSEMBLY__ */
41 #define AT91_MATRIX_ULBT_INFINITE (0 << 0)
42 #define AT91_MATRIX_ULBT_SINGLE (1 << 0)
43 #define AT91_MATRIX_ULBT_FOUR (2 << 0)
44 #define AT91_MATRIX_ULBT_EIGHT (3 << 0)
45 #define AT91_MATRIX_ULBT_SIXTEEN (4 << 0)
46 #define AT91_MATRIX_ULBT_THIRTYTWO (5 << 0)
47 #define AT91_MATRIX_ULBT_SIXTYFOUR (6 << 0)
48 #define AT91_MATRIX_ULBT_128 (7 << 0)
50 #define AT91_MATRIX_DEFMSTR_TYPE_NONE (0 << 16)
51 #define AT91_MATRIX_DEFMSTR_TYPE_LAST (1 << 16)
52 #define AT91_MATRIX_DEFMSTR_TYPE_FIXED (2 << 16)
53 #define AT91_MATRIX_FIXED_DEFMSTR_SHIFT 18
55 #define AT91_MATRIX_M0PR_SHIFT 0
56 #define AT91_MATRIX_M1PR_SHIFT 4
57 #define AT91_MATRIX_M2PR_SHIFT 8
58 #define AT91_MATRIX_M3PR_SHIFT 12
59 #define AT91_MATRIX_M4PR_SHIFT 16
60 #define AT91_MATRIX_M5PR_SHIFT 20
61 #define AT91_MATRIX_M6PR_SHIFT 24
62 #define AT91_MATRIX_M7PR_SHIFT 28
64 #define AT91_MATRIX_M8PR_SHIFT 0 /* register B */
65 #define AT91_MATRIX_M9PR_SHIFT 4 /* register B */
66 #define AT91_MATRIX_M10PR_SHIFT 8 /* register B */
67 #define AT91_MATRIX_M11PR_SHIFT 12 /* register B */
69 #define AT91_MATRIX_RCB0 (1 << 0)
70 #define AT91_MATRIX_RCB1 (1 << 1)
71 #define AT91_MATRIX_RCB2 (1 << 2)
72 #define AT91_MATRIX_RCB3 (1 << 3)
73 #define AT91_MATRIX_RCB4 (1 << 4)
74 #define AT91_MATRIX_RCB5 (1 << 5)
75 #define AT91_MATRIX_RCB6 (1 << 6)
76 #define AT91_MATRIX_RCB7 (1 << 7)
77 #define AT91_MATRIX_RCB8 (1 << 8)
78 #define AT91_MATRIX_RCB9 (1 << 9)
79 #define AT91_MATRIX_RCB10 (1 << 10)
81 #define AT91_MATRIX_EBI_CS1A_SMC (0 << 1)
82 #define AT91_MATRIX_EBI_CS1A_SDRAMC (1 << 1)
83 #define AT91_MATRIX_EBI_CS3A_SMC (0 << 3)
84 #define AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA (1 << 3)
85 #define AT91_MATRIX_EBI_DBPU_ON (0 << 8)
86 #define AT91_MATRIX_EBI_DBPU_OFF (1 << 8)
87 #define AT91_MATRIX_EBI_DBPD_ON (0 << 9)
88 #define AT91_MATRIX_EBI_DBPD_OFF (1 << 9)
89 #define AT91_MATRIX_EBI_VDDIOMSEL_1_8V (0 << 16)
90 #define AT91_MATRIX_EBI_VDDIOMSEL_3_3V (1 << 16)
91 #define AT91_MATRIX_EBI_EBI_IOSR_REDUCED (0 << 17)
92 #define AT91_MATRIX_EBI_EBI_IOSR_NORMAL (1 << 17)
93 #define AT91_MATRIX_NFD0_ON_D0 (0 << 24)
94 #define AT91_MATRIX_NFD0_ON_D16 (1 << 24)
95 #define AT91_MATRIX_MP_OFF (0 << 25)
96 #define AT91_MATRIX_MP_ON (1 << 25)