2 * (C) Copyright 2016 Google, Inc
4 * SPDX-License-Identifier: GPL-2.0+
9 #include <asm/arch/wdt.h>
10 #include <linux/err.h>
12 u32 ast_reset_mode_from_flags(ulong flags)
14 return flags & WDT_CTRL_RESET_MASK;
17 u32 ast_reset_mask_from_flags(ulong flags)
22 ulong ast_flags_from_reset_mode_mask(u32 reset_mode, u32 reset_mask)
24 ulong ret = reset_mode & WDT_CTRL_RESET_MASK;
26 if (ret == WDT_CTRL_RESET_SOC)
27 ret |= (reset_mask << 2);
33 void wdt_stop(struct ast_wdt *wdt)
35 clrbits_le32(&wdt->ctrl, WDT_CTRL_EN);
38 void wdt_start(struct ast_wdt *wdt, u32 timeout)
40 writel(timeout, &wdt->counter_reload_val);
41 writel(WDT_COUNTER_RESTART_VAL, &wdt->counter_restart);
43 * Setting CLK1MHZ bit is just for compatibility with ast2400 part.
44 * On ast2500 watchdog timer clock is fixed at 1MHz and the bit is
47 setbits_le32(&wdt->ctrl,
48 WDT_CTRL_EN | WDT_CTRL_RESET | WDT_CTRL_CLK1MHZ);
50 #endif /* CONFIG_WDT */
52 int ast_wdt_reset_masked(struct ast_wdt *wdt, u32 mask)
54 #ifdef CONFIG_ASPEED_AST2500
58 writel(mask, &wdt->reset_mask);
59 clrbits_le32(&wdt->ctrl,
60 WDT_CTRL_RESET_MASK << WDT_CTRL_RESET_MODE_SHIFT);
63 /* Wait for WDT to reset */
64 while (readl(&wdt->ctrl) & WDT_CTRL_EN)
74 struct ast_wdt *ast_get_wdt(u8 wdt_number)
76 if (wdt_number > CONFIG_WDT_NUM - 1)
77 return ERR_PTR(-EINVAL);
79 return (struct ast_wdt *)(WDT_BASE +
80 sizeof(struct ast_wdt) * wdt_number);