1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * GIC Initialization Routines.
6 * David Feng <fenghua@phytium.com.cn>
9 #include <asm-offsets.h>
11 #include <linux/linkage.h>
13 #include <asm/macro.h>
16 /*************************************************************************
18 * void gic_init_secure(DistributorBase);
20 * Initialize secure copy of GIC at EL3.
22 *************************************************************************/
23 ENTRY(gic_init_secure)
25 * Initialize Distributor
26 * x0: Distributor Base
28 #if defined(CONFIG_GICV3)
29 mov w9, #0x37 /* EnableGrp0 | EnableGrp1NS */
30 /* EnableGrp1S | ARE_S | ARE_NS */
31 str w9, [x0, GICD_CTLR] /* Secure GICD_CTLR */
32 ldr w9, [x0, GICD_TYPER]
33 and w10, w9, #0x1f /* ITLinesNumber */
34 cbz w10, 1f /* No SPIs */
35 add x11, x0, (GICD_IGROUPRn + 4)
36 add x12, x0, (GICD_IGROUPMODRn + 4)
38 0: str w9, [x11], #0x4
39 str wzr, [x12], #0x4 /* Config SPIs as Group1NS */
42 #elif defined(CONFIG_GICV2)
43 mov w9, #0x3 /* EnableGrp0 | EnableGrp1 */
44 str w9, [x0, GICD_CTLR] /* Secure GICD_CTLR */
45 ldr w9, [x0, GICD_TYPER]
46 and w10, w9, #0x1f /* ITLinesNumber */
47 cbz w10, 1f /* No SPIs */
48 add x11, x0, GICD_IGROUPRn
49 mov w9, #~0 /* Config SPIs as Grp1 */
51 0: str w9, [x11], #0x4
55 ldr x1, =GICC_BASE /* GICC_CTLR */
56 mov w0, #3 /* EnableGrp0 | EnableGrp1 */
59 mov w0, #1 << 7 /* allow NS access to GICC_PMR */
60 str w0, [x1, #4] /* GICC_PMR */
64 ENDPROC(gic_init_secure)
67 /*************************************************************************
69 * void gic_init_secure_percpu(DistributorBase, CpuInterfaceBase);
71 * void gic_init_secure_percpu(ReDistributorBase);
73 * Initialize secure copy of GIC at EL3.
75 *************************************************************************/
76 ENTRY(gic_init_secure_percpu)
77 #if defined(CONFIG_GICV3)
79 * Initialize ReDistributor
80 * x0: ReDistributor Base
84 bfi x10, x9, #24, #8 /* w10 is aff3:aff2:aff1:aff0 */
86 1: ldr x11, [x9, GICR_TYPER]
87 lsr x11, x11, #32 /* w11 is aff3:aff2:aff1:aff0 */
90 add x9, x9, #(2 << 16)
93 /* x9: ReDistributor Base Address of Current CPU */
95 ldr w11, [x9, GICR_WAKER]
96 and w11, w11, w10 /* Clear ProcessorSleep */
97 str w11, [x9, GICR_WAKER]
100 3: ldr w10, [x9, GICR_WAKER]
101 tbnz w10, #2, 3b /* Wait Children be Alive */
103 add x10, x9, #(1 << 16) /* SGI_Base */
105 str w11, [x10, GICR_IGROUPRn]
106 str wzr, [x10, GICR_IGROUPMODRn] /* SGIs|PPIs Group1NS */
107 mov w11, #0x1 /* Enable SGI 0 */
108 str w11, [x10, GICR_ISENABLERn]
110 switch_el x10, 3f, 2f, 1f
112 /* Initialize Cpu Interface */
114 orr x10, x10, #0xf /* SRE & Disable IRQ/FIQ Bypass & */
115 /* Allow EL2 access to ICC_SRE_EL2 */
119 mov x10, #0x3 /* EnableGrp1NS | EnableGrp1S */
120 msr ICC_IGRPEN1_EL3, x10
123 msr ICC_CTLR_EL3, xzr
127 orr x10, x10, #0xf /* SRE & Disable IRQ/FIQ Bypass & */
128 /* Allow EL1 access to ICC_SRE_EL1 */
132 msr ICC_CTLR_EL1, xzr /* NonSecure ICC_CTLR_EL1 */
135 mov x10, #0x1 << 7 /* Non-Secure access to ICC_PMR_EL1 */
138 #elif defined(CONFIG_GICV2)
140 * Initialize SGIs and PPIs
141 * x0: Distributor Base
142 * x1: Cpu Interface Base
144 mov w9, #~0 /* Config SGIs and PPIs as Grp1 */
145 str w9, [x0, GICD_IGROUPRn] /* GICD_IGROUPR0 */
146 mov w9, #0x1 /* Enable SGI 0 */
147 str w9, [x0, GICD_ISENABLERn]
149 /* Initialize Cpu Interface */
150 mov w9, #0x1e7 /* Disable IRQ/FIQ Bypass & */
151 /* Enable Ack Group1 Interrupt & */
152 /* EnableGrp0 & EnableGrp1 */
153 str w9, [x1, GICC_CTLR] /* Secure GICC_CTLR */
155 mov w9, #0x1 << 7 /* Non-Secure access to GICC_PMR */
156 str w9, [x1, GICC_PMR]
159 ENDPROC(gic_init_secure_percpu)
162 /*************************************************************************
164 * void gic_kick_secondary_cpus(DistributorBase);
166 * void gic_kick_secondary_cpus(void);
168 *************************************************************************/
169 ENTRY(gic_kick_secondary_cpus)
170 #if defined(CONFIG_GICV3)
172 msr ICC_ASGI1R_EL1, x9
174 #elif defined(CONFIG_GICV2)
176 movk w9, #0x100, lsl #16
177 str w9, [x0, GICD_SGIR]
180 ENDPROC(gic_kick_secondary_cpus)
183 /*************************************************************************
185 * void gic_wait_for_interrupt(CpuInterfaceBase);
187 * void gic_wait_for_interrupt(void);
189 * Wait for SGI 0 from master.
191 *************************************************************************/
192 ENTRY(gic_wait_for_interrupt)
193 #if defined(CONFIG_GICV3)
194 gic_wait_for_interrupt_m x9
195 #elif defined(CONFIG_GICV2)
196 gic_wait_for_interrupt_m x0, w9
199 ENDPROC(gic_wait_for_interrupt)