1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * (C) Copyright 2015 Freescale Semiconductor
5 * Extracted from gic_64.S
9 #include <linux/linkage.h>
10 #include <asm/macro.h>
12 /*************************************************************************
14 * void ccn504_add_masters_to_dvm(CCI_MN_BASE, CCI_MN_RNF_NODEID_LIST,
15 * CCI_MN_DVM_DOMAIN_CTL_SET);
17 * Add fully-coherent masters to DVM domain
19 *************************************************************************/
20 ENTRY(ccn504_add_masters_to_dvm)
23 * x1: CCI_MN_RNF_NODEID_LIST
24 * x2: CCI_MN_DVM_DOMAIN_CTL_SET
27 /* Add fully-coherent masters to DVM domain */
32 tst x11, x10 /* Wait for domain addition to complete */
36 ENDPROC(ccn504_add_masters_to_dvm)
38 /*************************************************************************
40 * void ccn504_set_qos(CCI_Sx_QOS_CONTROL_BASE, QoS Value);
42 * Initialize QoS settings for AR/AW override.
43 * Right now, this function sets the same QoS value for all RN-I ports
45 *************************************************************************/
48 * x0: CCI_Sx_QOS_CONTROL_BASE
52 /* Set all RN-I ports to QoS value denoted by x1 */
59 ENDPROC(ccn504_set_qos)
61 /*************************************************************************
63 * void ccn504_set_aux(CCI_AUX_CONTROL_BASE, Value);
65 * Initialize AUX control settings
67 *************************************************************************/
70 * x0: CCI_AUX_CONTROL_BASE
80 ENDPROC(ccn504_set_aux)