1 // SPDX-License-Identifier: GPL-2.0+
4 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
7 /* for now: just dummy functions to satisfy the linker */
13 * Flush range from all levels of d-cache/unified-cache.
14 * Affects the range [start, start + size - 1].
16 __weak void flush_cache(unsigned long start, unsigned long size)
18 flush_dcache_range(start, start + size);
22 * Default implementation:
23 * do a range flush for the entire range
25 __weak void flush_dcache_all(void)
31 * Default implementation of enable_caches()
32 * Real implementation should be in platform code
34 __weak void enable_caches(void)
36 puts("WARNING: Caches not enabled\n");
39 __weak void invalidate_dcache_range(unsigned long start, unsigned long stop)
41 /* An empty stub, real implementation should be in platform code */
43 __weak void flush_dcache_range(unsigned long start, unsigned long stop)
45 /* An empty stub, real implementation should be in platform code */
48 int check_cache_range(unsigned long start, unsigned long stop)
52 if (start & (CONFIG_SYS_CACHELINE_SIZE - 1))
55 if (stop & (CONFIG_SYS_CACHELINE_SIZE - 1))
59 warn_non_spl("CACHE: Misaligned operation at range [%08lx, %08lx]\n",
66 #ifdef CONFIG_SYS_NONCACHED_MEMORY
68 * Reserve one MMU section worth of address space below the malloc() area that
69 * will be mapped uncached.
71 static unsigned long noncached_start;
72 static unsigned long noncached_end;
73 static unsigned long noncached_next;
75 void noncached_init(void)
77 phys_addr_t start, end;
80 end = ALIGN(mem_malloc_start, MMU_SECTION_SIZE) - MMU_SECTION_SIZE;
81 size = ALIGN(CONFIG_SYS_NONCACHED_MEMORY, MMU_SECTION_SIZE);
84 debug("mapping memory %pa-%pa non-cached\n", &start, &end);
86 noncached_start = start;
88 noncached_next = start;
90 #ifndef CONFIG_SYS_DCACHE_OFF
91 mmu_set_region_dcache_behaviour(noncached_start, size, DCACHE_OFF);
95 phys_addr_t noncached_alloc(size_t size, size_t align)
97 phys_addr_t next = ALIGN(noncached_next, align);
99 if (next >= noncached_end || (noncached_end - next) < size)
102 debug("allocated %zu bytes of uncached memory @%pa\n", size, &next);
103 noncached_next = next + size;
107 #endif /* CONFIG_SYS_NONCACHED_MEMORY */
109 #if CONFIG_IS_ENABLED(SYS_THUMB_BUILD)
110 void invalidate_l2_cache(void)
112 unsigned int val = 0;
114 asm volatile("mcr p15, 1, %0, c15, c11, 0 @ invl l2 cache"
115 : : "r" (val) : "cc");