3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * SPDX-License-Identifier: GPL-2.0+
9 #include <asm/system.h>
10 #include <asm/cache.h>
11 #include <linux/compiler.h>
13 #if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF))
15 DECLARE_GLOBAL_DATA_PTR;
17 __weak void arm_init_before_mmu(void)
21 __weak void arm_init_domains(void)
25 static void cp_delay (void)
29 /* copro seems to need some delay between reading and writing */
30 for (i = 0; i < 100; i++)
32 asm volatile("" : : : "memory");
35 void set_section_dcache(int section, enum dcache_option option)
37 u32 *page_table = (u32 *)gd->arch.tlb_addr;
40 value = (section << MMU_SECTION_SHIFT) | (3 << 10);
42 page_table[section] = value;
45 __weak void mmu_page_table_flush(unsigned long start, unsigned long stop)
47 debug("%s: Warning: not implemented\n", __func__);
50 void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size,
51 enum dcache_option option)
53 u32 *page_table = (u32 *)gd->arch.tlb_addr;
54 unsigned long upto, end;
56 end = ALIGN(start + size, MMU_SECTION_SIZE) >> MMU_SECTION_SHIFT;
57 start = start >> MMU_SECTION_SHIFT;
58 debug("%s: start=%pa, size=%zu, option=%d\n", __func__, &start, size,
60 for (upto = start; upto < end; upto++)
61 set_section_dcache(upto, option);
62 mmu_page_table_flush((u32)&page_table[start], (u32)&page_table[end]);
65 __weak void dram_bank_mmu_setup(int bank)
70 debug("%s: bank: %d\n", __func__, bank);
71 for (i = bd->bi_dram[bank].start >> 20;
72 i < (bd->bi_dram[bank].start >> 20) + (bd->bi_dram[bank].size >> 20);
74 #if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH)
75 set_section_dcache(i, DCACHE_WRITETHROUGH);
76 #elif defined(CONFIG_SYS_ARM_CACHE_WRITEALLOC)
77 set_section_dcache(i, DCACHE_WRITEALLOC);
79 set_section_dcache(i, DCACHE_WRITEBACK);
84 /* to activate the MMU we need to set up virtual memory: use 1M areas */
85 static inline void mmu_setup(void)
90 arm_init_before_mmu();
91 /* Set up an identity-mapping for all 4GB, rw for everyone */
92 for (i = 0; i < 4096; i++)
93 set_section_dcache(i, DCACHE_OFF);
95 for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
96 dram_bank_mmu_setup(i);
101 reg = gd->arch.tlb_addr & TTBR0_BASE_ADDR_MASK;
102 #if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH)
103 reg |= TTBR0_RGN_WT | TTBR0_IRGN_WT;
104 #elif defined(CONFIG_SYS_ARM_CACHE_WRITEALLOC)
105 reg |= TTBR0_RGN_WBWA | TTBR0_IRGN_WBWA;
107 reg |= TTBR0_RGN_WB | TTBR0_IRGN_WB;
109 asm volatile("mcr p15, 0, %0, c2, c0, 0"
110 : : "r" (reg) : "memory");
112 /* Copy the page table address to cp15 */
113 asm volatile("mcr p15, 0, %0, c2, c0, 0"
114 : : "r" (gd->arch.tlb_addr) : "memory");
116 /* Set the access control to all-supervisor */
117 asm volatile("mcr p15, 0, %0, c3, c0, 0"
122 /* and enable the mmu */
123 reg = get_cr(); /* get control reg. */
128 static int mmu_enabled(void)
130 return get_cr() & CR_M;
133 /* cache_bit must be either CR_I or CR_C */
134 static void cache_enable(uint32_t cache_bit)
138 /* The data cache is not active unless the mmu is enabled too */
139 if ((cache_bit == CR_C) && !mmu_enabled())
141 reg = get_cr(); /* get control reg. */
143 set_cr(reg | cache_bit);
146 /* cache_bit must be either CR_I or CR_C */
147 static void cache_disable(uint32_t cache_bit)
154 if (cache_bit == CR_C) {
155 /* if cache isn;t enabled no need to disable */
156 if ((reg & CR_C) != CR_C)
158 /* if disabling data cache, disable mmu too */
163 if (cache_bit == (CR_C | CR_M))
165 set_cr(reg & ~cache_bit);
169 #ifdef CONFIG_SYS_ICACHE_OFF
170 void icache_enable (void)
175 void icache_disable (void)
180 int icache_status (void)
182 return 0; /* always off */
185 void icache_enable(void)
190 void icache_disable(void)
195 int icache_status(void)
197 return (get_cr() & CR_I) != 0;
201 #ifdef CONFIG_SYS_DCACHE_OFF
202 void dcache_enable (void)
207 void dcache_disable (void)
212 int dcache_status (void)
214 return 0; /* always off */
217 void dcache_enable(void)
222 void dcache_disable(void)
227 int dcache_status(void)
229 return (get_cr() & CR_C) != 0;