1 // SPDX-License-Identifier: GPL-2.0+
4 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
8 #include <asm/system.h>
10 #include <linux/compiler.h>
11 #include <asm/armv7_mpu.h>
13 #if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF))
15 DECLARE_GLOBAL_DATA_PTR;
17 #ifdef CONFIG_SYS_ARM_MMU
18 __weak void arm_init_before_mmu(void)
22 __weak void arm_init_domains(void)
26 void set_section_dcache(int section, enum dcache_option option)
28 #ifdef CONFIG_ARMV7_LPAE
29 u64 *page_table = (u64 *)gd->arch.tlb_addr;
30 /* Need to set the access flag to not fault */
31 u64 value = TTB_SECT_AP | TTB_SECT_AF;
33 u32 *page_table = (u32 *)gd->arch.tlb_addr;
34 u32 value = TTB_SECT_AP;
37 /* Add the page offset */
38 value |= ((u32)section << MMU_SECTION_SHIFT);
40 /* Add caching bits */
44 page_table[section] = value;
47 __weak void mmu_page_table_flush(unsigned long start, unsigned long stop)
49 debug("%s: Warning: not implemented\n", __func__);
52 void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size,
53 enum dcache_option option)
55 #ifdef CONFIG_ARMV7_LPAE
56 u64 *page_table = (u64 *)gd->arch.tlb_addr;
58 u32 *page_table = (u32 *)gd->arch.tlb_addr;
60 unsigned long startpt, stoppt;
61 unsigned long upto, end;
63 end = ALIGN(start + size, MMU_SECTION_SIZE) >> MMU_SECTION_SHIFT;
64 start = start >> MMU_SECTION_SHIFT;
65 #ifdef CONFIG_ARMV7_LPAE
66 debug("%s: start=%pa, size=%zu, option=%llx\n", __func__, &start, size,
69 debug("%s: start=%pa, size=%zu, option=0x%x\n", __func__, &start, size,
72 for (upto = start; upto < end; upto++)
73 set_section_dcache(upto, option);
76 * Make sure range is cache line aligned
77 * Only CPU maintains page tables, hence it is safe to always
78 * flush complete cache lines...
81 startpt = (unsigned long)&page_table[start];
82 startpt &= ~(CONFIG_SYS_CACHELINE_SIZE - 1);
83 stoppt = (unsigned long)&page_table[end];
84 stoppt = ALIGN(stoppt, CONFIG_SYS_CACHELINE_SIZE);
85 mmu_page_table_flush(startpt, stoppt);
88 __weak void dram_bank_mmu_setup(int bank)
93 debug("%s: bank: %d\n", __func__, bank);
94 for (i = bd->bi_dram[bank].start >> MMU_SECTION_SHIFT;
95 i < (bd->bi_dram[bank].start >> MMU_SECTION_SHIFT) +
96 (bd->bi_dram[bank].size >> MMU_SECTION_SHIFT);
98 #if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH)
99 set_section_dcache(i, DCACHE_WRITETHROUGH);
100 #elif defined(CONFIG_SYS_ARM_CACHE_WRITEALLOC)
101 set_section_dcache(i, DCACHE_WRITEALLOC);
103 set_section_dcache(i, DCACHE_WRITEBACK);
108 /* to activate the MMU we need to set up virtual memory: use 1M areas */
109 static inline void mmu_setup(void)
114 arm_init_before_mmu();
115 /* Set up an identity-mapping for all 4GB, rw for everyone */
116 for (i = 0; i < ((4096ULL * 1024 * 1024) >> MMU_SECTION_SHIFT); i++)
117 set_section_dcache(i, DCACHE_OFF);
119 for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
120 dram_bank_mmu_setup(i);
123 #if defined(CONFIG_ARMV7_LPAE) && __LINUX_ARM_ARCH__ != 4
124 /* Set up 4 PTE entries pointing to our 4 1GB page tables */
125 for (i = 0; i < 4; i++) {
126 u64 *page_table = (u64 *)(gd->arch.tlb_addr + (4096 * 4));
127 u64 tpt = gd->arch.tlb_addr + (4096 * i);
128 page_table[i] = tpt | TTB_PAGETABLE;
132 #if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH)
133 reg |= TTBCR_ORGN0_WT | TTBCR_IRGN0_WT;
134 #elif defined(CONFIG_SYS_ARM_CACHE_WRITEALLOC)
135 reg |= TTBCR_ORGN0_WBWA | TTBCR_IRGN0_WBWA;
137 reg |= TTBCR_ORGN0_WBNWA | TTBCR_IRGN0_WBNWA;
141 /* Set HTCR to enable LPAE */
142 asm volatile("mcr p15, 4, %0, c2, c0, 2"
143 : : "r" (reg) : "memory");
145 asm volatile("mcrr p15, 4, %0, %1, c2"
147 : "r"(gd->arch.tlb_addr + (4096 * 4)), "r"(0)
150 asm volatile("mcr p15, 4, %0, c10, c2, 0"
151 : : "r" (MEMORY_ATTRIBUTES) : "memory");
153 /* Set TTBCR to enable LPAE */
154 asm volatile("mcr p15, 0, %0, c2, c0, 2"
155 : : "r" (reg) : "memory");
156 /* Set 64-bit TTBR0 */
157 asm volatile("mcrr p15, 0, %0, %1, c2"
159 : "r"(gd->arch.tlb_addr + (4096 * 4)), "r"(0)
162 asm volatile("mcr p15, 0, %0, c10, c2, 0"
163 : : "r" (MEMORY_ATTRIBUTES) : "memory");
165 #elif defined(CONFIG_CPU_V7A)
167 /* Set HTCR to disable LPAE */
168 asm volatile("mcr p15, 4, %0, c2, c0, 2"
169 : : "r" (0) : "memory");
171 /* Set TTBCR to disable LPAE */
172 asm volatile("mcr p15, 0, %0, c2, c0, 2"
173 : : "r" (0) : "memory");
176 reg = gd->arch.tlb_addr & TTBR0_BASE_ADDR_MASK;
177 #if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH)
178 reg |= TTBR0_RGN_WT | TTBR0_IRGN_WT;
179 #elif defined(CONFIG_SYS_ARM_CACHE_WRITEALLOC)
180 reg |= TTBR0_RGN_WBWA | TTBR0_IRGN_WBWA;
182 reg |= TTBR0_RGN_WB | TTBR0_IRGN_WB;
184 asm volatile("mcr p15, 0, %0, c2, c0, 0"
185 : : "r" (reg) : "memory");
187 /* Copy the page table address to cp15 */
188 asm volatile("mcr p15, 0, %0, c2, c0, 0"
189 : : "r" (gd->arch.tlb_addr) : "memory");
191 /* Set the access control to all-supervisor */
192 asm volatile("mcr p15, 0, %0, c3, c0, 0"
197 /* and enable the mmu */
198 reg = get_cr(); /* get control reg. */
202 static int mmu_enabled(void)
204 return get_cr() & CR_M;
206 #endif /* CONFIG_SYS_ARM_MMU */
208 /* cache_bit must be either CR_I or CR_C */
209 static void cache_enable(uint32_t cache_bit)
213 /* The data cache is not active unless the mmu/mpu is enabled too */
214 #ifdef CONFIG_SYS_ARM_MMU
215 if ((cache_bit == CR_C) && !mmu_enabled())
217 #elif defined(CONFIG_SYS_ARM_MPU)
218 if ((cache_bit == CR_C) && !mpu_enabled()) {
219 printf("Consider enabling MPU before enabling caches\n");
223 reg = get_cr(); /* get control reg. */
224 set_cr(reg | cache_bit);
227 /* cache_bit must be either CR_I or CR_C */
228 static void cache_disable(uint32_t cache_bit)
234 if (cache_bit == CR_C) {
235 /* if cache isn;t enabled no need to disable */
236 if ((reg & CR_C) != CR_C)
238 /* if disabling data cache, disable mmu too */
243 if (cache_bit == (CR_C | CR_M))
245 set_cr(reg & ~cache_bit);
249 #ifdef CONFIG_SYS_ICACHE_OFF
250 void icache_enable (void)
255 void icache_disable (void)
260 int icache_status (void)
262 return 0; /* always off */
265 void icache_enable(void)
270 void icache_disable(void)
275 int icache_status(void)
277 return (get_cr() & CR_I) != 0;
281 #ifdef CONFIG_SYS_DCACHE_OFF
282 void dcache_enable (void)
287 void dcache_disable (void)
292 int dcache_status (void)
294 return 0; /* always off */
297 void dcache_enable(void)
302 void dcache_disable(void)
307 int dcache_status(void)
309 return (get_cr() & CR_C) != 0;