arch/arm/include/asm/ti-common/ti-edma3.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Enhanced Direct Memory Access (EDMA3) Controller
   4  *
   5  * (C) Copyright 2014
   6  *     Texas Instruments Incorporated, <www.ti.com>
   7  */
   8
   9 #ifndef _EDMA3_H_
  10 #define _EDMA3_H_
  11
  12 #ifndef __ASSEMBLY__
  13 #include <linux/bitops.h>
  14 #endif
  15 #include <linux/stddef.h>
  16
  17 #define EDMA3_PARSET_NULL_LINK                  0xffff
  18
  19 /*
  20  * All parameter RAM set options
  21  * opt field in edma3_param_set_config structure
  22  */
  23 #define EDMA3_SLOPT_PRIV_LEVEL                  BIT(31)
  24 #define EDMA3_SLOPT_PRIV_ID(id)                 ((0xf & (id)) << 24)
  25 #define EDMA3_SLOPT_INTERM_COMP_CHAIN_ENB       BIT(23)
  26 #define EDMA3_SLOPT_TRANS_COMP_CHAIN_ENB        BIT(22)
  27 #define EDMA3_SLOPT_INTERM_COMP_INT_ENB         BIT(21)
  28 #define EDMA3_SLOPT_TRANS_COMP_INT_ENB          BIT(20)
  29 #define EDMA3_SLOPT_COMP_CODE(code)             ((0x3f & (code)) << 12)
  30 #define EDMA3_SLOPT_FIFO_WIDTH_8                0
  31 #define EDMA3_SLOPT_FIFO_WIDTH_16               (1 << 8)
  32 #define EDMA3_SLOPT_FIFO_WIDTH_32               (2 << 8)
  33 #define EDMA3_SLOPT_FIFO_WIDTH_64               (3 << 8)
  34 #define EDMA3_SLOPT_FIFO_WIDTH_128              (4 << 8)
  35 #define EDMA3_SLOPT_FIFO_WIDTH_256              (5 << 8)
  36 #define EDMA3_SLOPT_FIFO_WIDTH_SET(w)           ((w & 0x7) << 8)
  37 #define EDMA3_SLOPT_STATIC                      BIT(3)
  38 #define EDMA3_SLOPT_AB_SYNC                     BIT(2)
  39 #define EDMA3_SLOPT_DST_ADDR_CONST_MODE         BIT(1)
  40 #define EDMA3_SLOPT_SRC_ADDR_CONST_MODE         BIT(0)
  41
  42 enum edma3_address_mode {
  43         INCR = 0,
  44         FIFO = 1
  45 };
  46
  47 enum edma3_fifo_width {
  48         W8BIT = 0,
  49         W16BIT = 1,
  50         W32BIT = 2,
  51         W64BIT = 3,
  52         W128BIT = 4,
  53         W256BIT = 5
  54 };
  55
  56 enum edma3_sync_dimension {
  57         ASYNC = 0,
  58         ABSYNC = 1
  59 };
  60
  61 /* PaRAM slots are laid out like this */
  62 struct edma3_slot_layout {
  63         u32 opt;
  64         u32 src;
  65         u32 a_b_cnt;
  66         u32 dst;
  67         u32 src_dst_bidx;
  68         u32 link_bcntrld;
  69         u32 src_dst_cidx;
  70         u32 ccnt;
  71 } __packed;
  72
  73 /*
  74  * Use this to assign trigger word number of edma3_slot_layout struct.
  75  * trigger_word_name - is the exact name from edma3_slot_layout.
  76  */
  77 #define EDMA3_TWORD(trigger_word_name)\
  78                 (offsetof(struct edma3_slot_layout, trigger_word_name) / 4)
  79
  80 struct edma3_slot_config {
  81         u32 opt;
  82         u32 src;
  83         u32 dst;
  84         int bcnt;
  85         int acnt;
  86         int ccnt;
  87         int src_bidx;
  88         int dst_bidx;
  89         int src_cidx;
  90         int dst_cidx;
  91         int bcntrld;
  92         int link;
  93 };
  94
  95 struct edma3_channel_config {
  96         int slot;
  97         int chnum;
  98         int complete_code;      /* indicate pending complete interrupt */
  99         int trigger_slot_word;  /* only used for qedma */
 100 };
 101
 102 void qedma3_start(u32 base, struct edma3_channel_config *cfg);
 103 void qedma3_stop(u32 base, struct edma3_channel_config *cfg);
 104 void edma3_slot_configure(u32 base, int slot, struct edma3_slot_config *cfg);
 105 int edma3_check_for_transfer(u32 base, struct edma3_channel_config *cfg);
 106 void edma3_write_slot(u32 base, int slot, struct edma3_slot_layout *param);
 107 void edma3_read_slot(u32 base, int slot, struct edma3_slot_layout *param);
 108
 109 void edma3_set_dest(u32 base, int slot, u32 dst, enum edma3_address_mode mode,
 110                     enum edma3_fifo_width width);
 111 void edma3_set_dest_index(u32 base, unsigned slot, int bidx, int cidx);
 112 void edma3_set_dest_addr(u32 base, int slot, u32 dst);
 113
 114 void edma3_set_src(u32 base, int slot, u32 src, enum edma3_address_mode mode,
 115                    enum edma3_fifo_width width);
 116 void edma3_set_src_index(u32 base, unsigned slot, int bidx, int cidx);
 117 void edma3_set_src_addr(u32 base, int slot, u32 src);
 118
 119 void edma3_set_transfer_params(u32 base, int slot, int acnt,
 120                                int bcnt, int ccnt, u16 bcnt_rld,
 121                                enum edma3_sync_dimension sync_mode);
 122 void edma3_transfer(unsigned long edma3_base_addr, unsigned int
 123                 edma_slot_num, void *dst, void *src, size_t len);
 124 void edma3_fill(unsigned long edma3_base_addr, unsigned int edma_slot_num,
 125                 void *dst, u8 val, size_t len);
 126
 127 #endif