1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Multicore Navigator definitions
5 * (C) Copyright 2012-2014
6 * Texas Instruments Incorporated, <www.ti.com>
9 #ifndef _KEYSTONE_NAV_H_
10 #define _KEYSTONE_NAV_H_
12 #include <asm/arch/hardware.h>
17 #define QM_DESC_TYPE_HOST 0
18 #define QM_DESC_PSINFO_IN_DESCR 0
19 #define QM_DESC_DEFAULT_DESCINFO (QM_DESC_TYPE_HOST << 30) | \
20 (QM_DESC_PSINFO_IN_DESCR << 22)
23 #define QM_DESC_PINFO_EPIB 1
24 #define QM_DESC_PINFO_RETURN_OWN 1
25 #define QM_DESC_DEFAULT_PINFO (QM_DESC_PINFO_EPIB << 31) | \
26 (QM_DESC_PINFO_RETURN_OWN << 15)
40 struct descr_mem_setup_reg {
55 /* QM module addresses */
56 u32 stat_cfg; /* status and config */
57 struct qm_reg_queue *queue; /* management region */
58 u32 mngr_vbusm; /* management region (VBUSM) */
59 u32 i_lram; /* internal linking RAM */
60 struct qm_reg_queue *proxy;
62 struct qm_cfg_reg *mngr_cfg;
63 /* Queue manager config region */
64 u32 intd_cfg; /* QMSS INTD config region */
65 struct descr_mem_setup_reg *desc_mem;
66 /* descritor memory setup region*/
68 u32 pdsp_cmd; /* PDSP1 command interface */
69 u32 pdsp_ctl; /* PDSP1 control registers */
71 /* QM configuration parameters */
94 void qm_push(struct qm_host_desc *hd, u32 qnum);
95 struct qm_host_desc *qm_pop(u32 qnum);
97 void qm_buff_push(struct qm_host_desc *hd, u32 qnum,
98 void *buff_ptr, u32 buff_len);
100 struct qm_host_desc *qm_pop_from_free_pool(void);
101 void queue_close(u32 qnum);
106 #define CPDMA_REG_VAL_MAKE_RX_FLOW_A(einfo, psinfo, rxerr, desc, \
107 psloc, sopoff, qmgr, qnum) \
108 (((einfo & 1) << 30) | \
109 ((psinfo & 1) << 29) | \
110 ((rxerr & 1) << 28) | \
111 ((desc & 3) << 26) | \
112 ((psloc & 1) << 25) | \
113 ((sopoff & 0x1ff) << 16) | \
114 ((qmgr & 3) << 12) | \
115 ((qnum & 0xfff) << 0))
117 #define CPDMA_REG_VAL_MAKE_RX_FLOW_D(fd0qm, fd0qnum, fd1qm, fd1qnum) \
118 (((fd0qm & 3) << 28) | \
119 ((fd0qnum & 0xfff) << 16) | \
120 ((fd1qm & 3) << 12) | \
121 ((fd1qnum & 0xfff) << 0))
123 #define CPDMA_CHAN_A_ENABLE ((u32)1 << 31)
124 #define CPDMA_CHAN_A_TDOWN (1 << 30)
125 #define TDOWN_TIMEOUT_COUNT 100
127 struct global_ctl_regs {
130 u32 emulation_control;
131 u32 priority_control;
135 struct tx_chan_regs {
141 struct rx_chan_regs {
146 struct rx_flow_regs {
155 struct global_ctl_regs *global;
156 struct tx_chan_regs *tx_ch;
158 struct rx_chan_regs *rx_ch;
161 struct rx_flow_regs *rx_flows;
168 u32 rx_flow; /* flow that is used for RX */
171 extern struct pktdma_cfg netcp_pktdma;
174 * packet dma user allocates memory for rx buffers
175 * and describe it in the following structure
177 struct rx_buff_desc {
184 int ksnav_close(struct pktdma_cfg *pktdma);
185 int ksnav_init(struct pktdma_cfg *pktdma, struct rx_buff_desc *rx_buffers);
186 int ksnav_send(struct pktdma_cfg *pktdma, u32 *pkt, int num_bytes, u32 swinfo2);
187 void *ksnav_recv(struct pktdma_cfg *pktdma, u32 **pkt, int *num_bytes);
188 void ksnav_release_rxhd(struct pktdma_cfg *pktdma, void *hd);
190 #endif /* _KEYSTONE_NAV_H_ */