1 #ifndef __ASM_ARM_SYSTEM_H
2 #define __ASM_ARM_SYSTEM_H
5 #include <linux/compiler.h>
10 * SCTLR_EL1/SCTLR_EL2/SCTLR_EL3 bits definitions
12 #define CR_M (1 << 0) /* MMU enable */
13 #define CR_A (1 << 1) /* Alignment abort enable */
14 #define CR_C (1 << 2) /* Dcache enable */
15 #define CR_SA (1 << 3) /* Stack Alignment Check Enable */
16 #define CR_I (1 << 12) /* Icache enable */
17 #define CR_WXN (1 << 19) /* Write Permision Imply XN */
18 #define CR_EE (1 << 25) /* Exception (Big) Endian */
22 u64 get_page_table_size(void);
23 #define PGTABLE_SIZE get_page_table_size()
26 #define MMU_SECTION_SHIFT 21
27 #define MMU_SECTION_SIZE (1 << MMU_SECTION_SHIFT)
35 "isb" : : : "memory"); \
40 "wfi" : : : "memory"); \
43 static inline unsigned int current_el(void)
46 asm volatile("mrs %0, CurrentEL" : "=r" (el) : : "cc");
50 static inline unsigned int get_sctlr(void)
56 asm volatile("mrs %0, sctlr_el1" : "=r" (val) : : "cc");
58 asm volatile("mrs %0, sctlr_el2" : "=r" (val) : : "cc");
60 asm volatile("mrs %0, sctlr_el3" : "=r" (val) : : "cc");
65 static inline void set_sctlr(unsigned int val)
71 asm volatile("msr sctlr_el1, %0" : : "r" (val) : "cc");
73 asm volatile("msr sctlr_el2, %0" : : "r" (val) : "cc");
75 asm volatile("msr sctlr_el3, %0" : : "r" (val) : "cc");
80 static inline unsigned long read_mpidr(void)
84 asm volatile("mrs %0, mpidr_el1" : "=r" (val));
91 void __asm_flush_dcache_all(void);
92 void __asm_invalidate_dcache_all(void);
93 void __asm_flush_dcache_range(u64 start, u64 end);
94 void __asm_invalidate_tlb_all(void);
95 void __asm_invalidate_icache_all(void);
96 int __asm_flush_l3_cache(void);
97 void __asm_switch_ttbr(u64 new_ttbr);
99 void armv8_switch_to_el2(void);
100 void armv8_switch_to_el1(void);
102 void gic_send_sgi(unsigned long sgino);
103 void wait_for_wakeup(void);
104 void protect_secure_region(void);
105 void smp_kick_all_cpus(void);
107 void flush_l3_cache(void);
110 *Issue a hypervisor call in accordance with ARM "SMC Calling convention",
113 * @args: input and output arguments
116 void hvc_call(struct pt_regs *args);
119 *Issue a secure monitor call in accordance with ARM "SMC Calling convention",
122 * @args: input and output arguments
125 void smc_call(struct pt_regs *args);
127 #endif /* __ASSEMBLY__ */
129 #else /* CONFIG_ARM64 */
133 #define CPU_ARCH_UNKNOWN 0
134 #define CPU_ARCH_ARMv3 1
135 #define CPU_ARCH_ARMv4 2
136 #define CPU_ARCH_ARMv4T 3
137 #define CPU_ARCH_ARMv5 4
138 #define CPU_ARCH_ARMv5T 5
139 #define CPU_ARCH_ARMv5TE 6
140 #define CPU_ARCH_ARMv5TEJ 7
141 #define CPU_ARCH_ARMv6 8
142 #define CPU_ARCH_ARMv7 9
145 * CR1 bits (CP#15 CR1)
147 #define CR_M (1 << 0) /* MMU enable */
148 #define CR_A (1 << 1) /* Alignment abort enable */
149 #define CR_C (1 << 2) /* Dcache enable */
150 #define CR_W (1 << 3) /* Write buffer enable */
151 #define CR_P (1 << 4) /* 32-bit exception handler */
152 #define CR_D (1 << 5) /* 32-bit data address range */
153 #define CR_L (1 << 6) /* Implementation defined */
154 #define CR_B (1 << 7) /* Big endian */
155 #define CR_S (1 << 8) /* System MMU protection */
156 #define CR_R (1 << 9) /* ROM MMU protection */
157 #define CR_F (1 << 10) /* Implementation defined */
158 #define CR_Z (1 << 11) /* Implementation defined */
159 #define CR_I (1 << 12) /* Icache enable */
160 #define CR_V (1 << 13) /* Vectors relocated to 0xffff0000 */
161 #define CR_RR (1 << 14) /* Round Robin cache replacement */
162 #define CR_L4 (1 << 15) /* LDR pc can set T bit */
163 #define CR_DT (1 << 16)
164 #define CR_IT (1 << 18)
165 #define CR_ST (1 << 19)
166 #define CR_FI (1 << 21) /* Fast interrupt (lower latency mode) */
167 #define CR_U (1 << 22) /* Unaligned access operation */
168 #define CR_XP (1 << 23) /* Extended page tables */
169 #define CR_VE (1 << 24) /* Vectored interrupts */
170 #define CR_EE (1 << 25) /* Exception (Big) Endian */
171 #define CR_TRE (1 << 28) /* TEX remap enable */
172 #define CR_AFE (1 << 29) /* Access flag enable */
173 #define CR_TE (1 << 30) /* Thumb exception enable */
176 #define PGTABLE_SIZE (4096 * 4)
180 * This is used to ensure the compiler did actually allocate the register we
181 * asked it for some inline assembly sequences. Apparently we can't trust
182 * the compiler from one version to another so a bit of paranoia won't hurt.
183 * This string is meant to be concatenated with the inline asm string and
184 * will cause compilation to stop on mismatch.
185 * (for details, see gcc PR 15089)
187 #define __asmeq(x, y) ".ifnc " x "," y " ; .err ; .endif\n\t"
192 * save_boot_params() - Save boot parameters before starting reset sequence
194 * If you provide this function it will be called immediately U-Boot starts,
195 * both for SPL and U-Boot proper.
197 * All registers are unchanged from U-Boot entry. No registers need be
200 * This is not a normal C function. There is no stack. Return by branching to
201 * save_boot_params_ret.
203 * void save_boot_params(u32 r0, u32 r1, u32 r2, u32 r3);
207 * save_boot_params_ret() - Return from save_boot_params()
209 * If you provide save_boot_params(), then you should jump back to this
210 * function when done. Try to preserve all registers.
212 * If your implementation of save_boot_params() is in C then it is acceptable
213 * to simply call save_boot_params_ret() at the end of your function. Since
214 * there is no link register set up, you cannot just exit the function. U-Boot
215 * will return to the (initialised) value of lr, and likely crash/hang.
217 * If your implementation of save_boot_params() is in assembler then you
218 * should use 'b' or 'bx' to return to save_boot_params_ret.
220 void save_boot_params_ret(void);
222 #define isb() __asm__ __volatile__ ("" : : : "memory")
224 #define nop() __asm__ __volatile__("mov\tr0,r0\t@ nop\n\t");
226 #ifdef __ARM_ARCH_7A__
227 #define wfi() __asm__ __volatile__ ("wfi" : : : "memory")
232 static inline unsigned int get_cr(void)
235 asm volatile("mrc p15, 0, %0, c1, c0, 0 @ get CR" : "=r" (val) : : "cc");
239 static inline void set_cr(unsigned int val)
241 asm volatile("mcr p15, 0, %0, c1, c0, 0 @ set CR"
242 : : "r" (val) : "cc");
246 static inline unsigned int get_dacr(void)
249 asm("mrc p15, 0, %0, c3, c0, 0 @ get DACR" : "=r" (val) : : "cc");
253 static inline void set_dacr(unsigned int val)
255 asm volatile("mcr p15, 0, %0, c3, c0, 0 @ set DACR"
256 : : "r" (val) : "cc");
261 /* Short-Descriptor Translation Table Level 1 Bits */
262 #define TTB_SECT_NS_MASK (1 << 19)
263 #define TTB_SECT_NG_MASK (1 << 17)
264 #define TTB_SECT_S_MASK (1 << 16)
265 /* Note: TTB AP bits are set elsewhere */
266 #define TTB_SECT_TEX(x) ((x & 0x7) << 12)
267 #define TTB_SECT_DOMAIN(x) ((x & 0xf) << 5)
268 #define TTB_SECT_XN_MASK (1 << 4)
269 #define TTB_SECT_C_MASK (1 << 3)
270 #define TTB_SECT_B_MASK (1 << 2)
271 #define TTB_SECT (2 << 0)
273 /* options available for data cache on each page */
275 DCACHE_OFF = TTB_SECT_DOMAIN(0) | TTB_SECT_XN_MASK | TTB_SECT,
276 DCACHE_WRITETHROUGH = DCACHE_OFF | TTB_SECT_C_MASK,
277 DCACHE_WRITEBACK = DCACHE_WRITETHROUGH | TTB_SECT_B_MASK,
278 DCACHE_WRITEALLOC = DCACHE_WRITEBACK | TTB_SECT_TEX(1),
281 /* options available for data cache on each page */
284 DCACHE_WRITETHROUGH = 0x1a,
285 DCACHE_WRITEBACK = 0x1e,
286 DCACHE_WRITEALLOC = 0x16,
290 /* Size of an MMU section */
292 MMU_SECTION_SHIFT = 20,
293 MMU_SECTION_SIZE = 1 << MMU_SECTION_SHIFT,
298 #define TTBR0_BASE_ADDR_MASK 0xFFFFC000
299 #define TTBR0_RGN_NC (0 << 3)
300 #define TTBR0_RGN_WBWA (1 << 3)
301 #define TTBR0_RGN_WT (2 << 3)
302 #define TTBR0_RGN_WB (3 << 3)
303 /* TTBR0[6] is IRGN[0] and TTBR[0] is IRGN[1] */
304 #define TTBR0_IRGN_NC (0 << 0 | 0 << 6)
305 #define TTBR0_IRGN_WBWA (0 << 0 | 1 << 6)
306 #define TTBR0_IRGN_WT (1 << 0 | 0 << 6)
307 #define TTBR0_IRGN_WB (1 << 0 | 1 << 6)
311 * Register an update to the page tables, and flush the TLB
313 * \param start start address of update in page table
314 * \param stop stop address of update in page table
316 void mmu_page_table_flush(unsigned long start, unsigned long stop);
318 #endif /* __ASSEMBLY__ */
320 #define arch_align_stack(x) (x)
322 #endif /* __KERNEL__ */
324 #endif /* CONFIG_ARM64 */
328 * Change the cache settings for a region.
330 * \param start start address of memory region to change
331 * \param size size of memory region to change
332 * \param option dcache option to select
334 void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size,
335 enum dcache_option option);
337 #ifdef CONFIG_SYS_NONCACHED_MEMORY
338 void noncached_init(void);
339 phys_addr_t noncached_alloc(size_t size, size_t align);
340 #endif /* CONFIG_SYS_NONCACHED_MEMORY */
342 #endif /* __ASSEMBLY__ */