1 #ifndef __ASM_ARM_SYSTEM_H
2 #define __ASM_ARM_SYSTEM_H
5 #include <linux/compiler.h>
10 * SCTLR_EL1/SCTLR_EL2/SCTLR_EL3 bits definitions
12 #define CR_M (1 << 0) /* MMU enable */
13 #define CR_A (1 << 1) /* Alignment abort enable */
14 #define CR_C (1 << 2) /* Dcache enable */
15 #define CR_SA (1 << 3) /* Stack Alignment Check Enable */
16 #define CR_I (1 << 12) /* Icache enable */
17 #define CR_WXN (1 << 19) /* Write Permision Imply XN */
18 #define CR_EE (1 << 25) /* Exception (Big) Endian */
22 u64 get_page_table_size(void);
23 #define PGTABLE_SIZE get_page_table_size()
26 #define MMU_SECTION_SHIFT 21
27 #define MMU_SECTION_SIZE (1 << MMU_SECTION_SHIFT)
29 /* These constants need to be synced to the MT_ types in asm/armv8/mmu.h */
32 DCACHE_WRITETHROUGH = 3 << 2,
33 DCACHE_WRITEBACK = 4 << 2,
34 DCACHE_WRITEALLOC = 4 << 2,
39 "isb" : : : "memory"); \
44 "wfi" : : : "memory"); \
47 static inline unsigned int current_el(void)
50 asm volatile("mrs %0, CurrentEL" : "=r" (el) : : "cc");
54 static inline unsigned int get_sctlr(void)
60 asm volatile("mrs %0, sctlr_el1" : "=r" (val) : : "cc");
62 asm volatile("mrs %0, sctlr_el2" : "=r" (val) : : "cc");
64 asm volatile("mrs %0, sctlr_el3" : "=r" (val) : : "cc");
69 static inline void set_sctlr(unsigned int val)
75 asm volatile("msr sctlr_el1, %0" : : "r" (val) : "cc");
77 asm volatile("msr sctlr_el2, %0" : : "r" (val) : "cc");
79 asm volatile("msr sctlr_el3, %0" : : "r" (val) : "cc");
84 static inline unsigned long read_mpidr(void)
88 asm volatile("mrs %0, mpidr_el1" : "=r" (val));
95 void __asm_flush_dcache_all(void);
96 void __asm_invalidate_dcache_all(void);
97 void __asm_flush_dcache_range(u64 start, u64 end);
98 void __asm_invalidate_tlb_all(void);
99 void __asm_invalidate_icache_all(void);
100 int __asm_flush_l3_cache(void);
101 void __asm_switch_ttbr(u64 new_ttbr);
103 void armv8_switch_to_el2(void);
104 void armv8_switch_to_el1(void);
106 void gic_send_sgi(unsigned long sgino);
107 void wait_for_wakeup(void);
108 void protect_secure_region(void);
109 void smp_kick_all_cpus(void);
111 void flush_l3_cache(void);
114 *Issue a hypervisor call in accordance with ARM "SMC Calling convention",
117 * @args: input and output arguments
120 void hvc_call(struct pt_regs *args);
123 *Issue a secure monitor call in accordance with ARM "SMC Calling convention",
126 * @args: input and output arguments
129 void smc_call(struct pt_regs *args);
131 void __noreturn psci_system_reset(bool smc);
133 #endif /* __ASSEMBLY__ */
135 #else /* CONFIG_ARM64 */
139 #define CPU_ARCH_UNKNOWN 0
140 #define CPU_ARCH_ARMv3 1
141 #define CPU_ARCH_ARMv4 2
142 #define CPU_ARCH_ARMv4T 3
143 #define CPU_ARCH_ARMv5 4
144 #define CPU_ARCH_ARMv5T 5
145 #define CPU_ARCH_ARMv5TE 6
146 #define CPU_ARCH_ARMv5TEJ 7
147 #define CPU_ARCH_ARMv6 8
148 #define CPU_ARCH_ARMv7 9
151 * CR1 bits (CP#15 CR1)
153 #define CR_M (1 << 0) /* MMU enable */
154 #define CR_A (1 << 1) /* Alignment abort enable */
155 #define CR_C (1 << 2) /* Dcache enable */
156 #define CR_W (1 << 3) /* Write buffer enable */
157 #define CR_P (1 << 4) /* 32-bit exception handler */
158 #define CR_D (1 << 5) /* 32-bit data address range */
159 #define CR_L (1 << 6) /* Implementation defined */
160 #define CR_B (1 << 7) /* Big endian */
161 #define CR_S (1 << 8) /* System MMU protection */
162 #define CR_R (1 << 9) /* ROM MMU protection */
163 #define CR_F (1 << 10) /* Implementation defined */
164 #define CR_Z (1 << 11) /* Implementation defined */
165 #define CR_I (1 << 12) /* Icache enable */
166 #define CR_V (1 << 13) /* Vectors relocated to 0xffff0000 */
167 #define CR_RR (1 << 14) /* Round Robin cache replacement */
168 #define CR_L4 (1 << 15) /* LDR pc can set T bit */
169 #define CR_DT (1 << 16)
170 #define CR_IT (1 << 18)
171 #define CR_ST (1 << 19)
172 #define CR_FI (1 << 21) /* Fast interrupt (lower latency mode) */
173 #define CR_U (1 << 22) /* Unaligned access operation */
174 #define CR_XP (1 << 23) /* Extended page tables */
175 #define CR_VE (1 << 24) /* Vectored interrupts */
176 #define CR_EE (1 << 25) /* Exception (Big) Endian */
177 #define CR_TRE (1 << 28) /* TEX remap enable */
178 #define CR_AFE (1 << 29) /* Access flag enable */
179 #define CR_TE (1 << 30) /* Thumb exception enable */
181 #if defined(CONFIG_ARMV7_LPAE) && !defined(PGTABLE_SIZE)
182 #define PGTABLE_SIZE (4096 * 5)
183 #elif !defined(PGTABLE_SIZE)
184 #define PGTABLE_SIZE (4096 * 4)
188 * This is used to ensure the compiler did actually allocate the register we
189 * asked it for some inline assembly sequences. Apparently we can't trust
190 * the compiler from one version to another so a bit of paranoia won't hurt.
191 * This string is meant to be concatenated with the inline asm string and
192 * will cause compilation to stop on mismatch.
193 * (for details, see gcc PR 15089)
195 #define __asmeq(x, y) ".ifnc " x "," y " ; .err ; .endif\n\t"
200 * save_boot_params() - Save boot parameters before starting reset sequence
202 * If you provide this function it will be called immediately U-Boot starts,
203 * both for SPL and U-Boot proper.
205 * All registers are unchanged from U-Boot entry. No registers need be
208 * This is not a normal C function. There is no stack. Return by branching to
209 * save_boot_params_ret.
211 * void save_boot_params(u32 r0, u32 r1, u32 r2, u32 r3);
215 * save_boot_params_ret() - Return from save_boot_params()
217 * If you provide save_boot_params(), then you should jump back to this
218 * function when done. Try to preserve all registers.
220 * If your implementation of save_boot_params() is in C then it is acceptable
221 * to simply call save_boot_params_ret() at the end of your function. Since
222 * there is no link register set up, you cannot just exit the function. U-Boot
223 * will return to the (initialised) value of lr, and likely crash/hang.
225 * If your implementation of save_boot_params() is in assembler then you
226 * should use 'b' or 'bx' to return to save_boot_params_ret.
228 void save_boot_params_ret(void);
230 #define isb() __asm__ __volatile__ ("" : : : "memory")
232 #define nop() __asm__ __volatile__("mov\tr0,r0\t@ nop\n\t");
234 #ifdef __ARM_ARCH_7A__
235 #define wfi() __asm__ __volatile__ ("wfi" : : : "memory")
240 static inline unsigned long get_cpsr(void)
244 asm volatile("mrs %0, cpsr" : "=r"(cpsr): );
248 static inline int is_hyp(void)
250 #ifdef CONFIG_ARMV7_LPAE
251 /* HYP mode requires LPAE ... */
252 return ((get_cpsr() & 0x1f) == 0x1a);
254 /* ... so without LPAE support we can optimize all hyp code away */
259 static inline unsigned int get_cr(void)
264 asm volatile("mrc p15, 4, %0, c1, c0, 0 @ get CR" : "=r" (val)
268 asm volatile("mrc p15, 0, %0, c1, c0, 0 @ get CR" : "=r" (val)
274 static inline void set_cr(unsigned int val)
277 asm volatile("mcr p15, 4, %0, c1, c0, 0 @ set CR" :
281 asm volatile("mcr p15, 0, %0, c1, c0, 0 @ set CR" :
287 static inline unsigned int get_dacr(void)
290 asm("mrc p15, 0, %0, c3, c0, 0 @ get DACR" : "=r" (val) : : "cc");
294 static inline void set_dacr(unsigned int val)
296 asm volatile("mcr p15, 0, %0, c3, c0, 0 @ set DACR"
297 : : "r" (val) : "cc");
301 #ifdef CONFIG_ARMV7_LPAE
302 /* Long-Descriptor Translation Table Level 1/2 Bits */
303 #define TTB_SECT_XN_MASK (1ULL << 54)
304 #define TTB_SECT_NG_MASK (1 << 11)
305 #define TTB_SECT_AF (1 << 10)
306 #define TTB_SECT_SH_MASK (3 << 8)
307 #define TTB_SECT_NS_MASK (1 << 5)
308 #define TTB_SECT_AP (1 << 6)
309 /* Note: TTB AP bits are set elsewhere */
310 #define TTB_SECT_MAIR(x) ((x & 0x7) << 2) /* Index into MAIR */
311 #define TTB_SECT (1 << 0)
312 #define TTB_PAGETABLE (3 << 0)
315 #define TTBCR_EAE (1 << 31)
316 #define TTBCR_T0SZ(x) ((x) << 0)
317 #define TTBCR_T1SZ(x) ((x) << 16)
318 #define TTBCR_USING_TTBR0 (TTBCR_T0SZ(0) | TTBCR_T1SZ(0))
319 #define TTBCR_IRGN0_NC (0 << 8)
320 #define TTBCR_IRGN0_WBWA (1 << 8)
321 #define TTBCR_IRGN0_WT (2 << 8)
322 #define TTBCR_IRGN0_WBNWA (3 << 8)
323 #define TTBCR_IRGN0_MASK (3 << 8)
324 #define TTBCR_ORGN0_NC (0 << 10)
325 #define TTBCR_ORGN0_WBWA (1 << 10)
326 #define TTBCR_ORGN0_WT (2 << 10)
327 #define TTBCR_ORGN0_WBNWA (3 << 10)
328 #define TTBCR_ORGN0_MASK (3 << 10)
329 #define TTBCR_SHARED_NON (0 << 12)
330 #define TTBCR_SHARED_OUTER (2 << 12)
331 #define TTBCR_SHARED_INNER (3 << 12)
332 #define TTBCR_EPD0 (0 << 7)
337 #define MEMORY_ATTRIBUTES ((0x00 << (0 * 8)) | (0x88 << (1 * 8)) | \
338 (0xcc << (2 * 8)) | (0xff << (3 * 8)))
340 /* options available for data cache on each page */
342 DCACHE_OFF = TTB_SECT | TTB_SECT_MAIR(0),
343 DCACHE_WRITETHROUGH = TTB_SECT | TTB_SECT_MAIR(1),
344 DCACHE_WRITEBACK = TTB_SECT | TTB_SECT_MAIR(2),
345 DCACHE_WRITEALLOC = TTB_SECT | TTB_SECT_MAIR(3),
347 #elif defined(CONFIG_CPU_V7)
348 /* Short-Descriptor Translation Table Level 1 Bits */
349 #define TTB_SECT_NS_MASK (1 << 19)
350 #define TTB_SECT_NG_MASK (1 << 17)
351 #define TTB_SECT_S_MASK (1 << 16)
352 /* Note: TTB AP bits are set elsewhere */
353 #define TTB_SECT_AP (3 << 10)
354 #define TTB_SECT_TEX(x) ((x & 0x7) << 12)
355 #define TTB_SECT_DOMAIN(x) ((x & 0xf) << 5)
356 #define TTB_SECT_XN_MASK (1 << 4)
357 #define TTB_SECT_C_MASK (1 << 3)
358 #define TTB_SECT_B_MASK (1 << 2)
359 #define TTB_SECT (2 << 0)
361 /* options available for data cache on each page */
363 DCACHE_OFF = TTB_SECT_DOMAIN(0) | TTB_SECT_XN_MASK | TTB_SECT,
364 DCACHE_WRITETHROUGH = DCACHE_OFF | TTB_SECT_C_MASK,
365 DCACHE_WRITEBACK = DCACHE_WRITETHROUGH | TTB_SECT_B_MASK,
366 DCACHE_WRITEALLOC = DCACHE_WRITEBACK | TTB_SECT_TEX(1),
369 #define TTB_SECT_AP (3 << 10)
370 /* options available for data cache on each page */
373 DCACHE_WRITETHROUGH = 0x1a,
374 DCACHE_WRITEBACK = 0x1e,
375 DCACHE_WRITEALLOC = 0x16,
379 /* Size of an MMU section */
381 #ifdef CONFIG_ARMV7_LPAE
382 MMU_SECTION_SHIFT = 21, /* 2MB */
384 MMU_SECTION_SHIFT = 20, /* 1MB */
386 MMU_SECTION_SIZE = 1 << MMU_SECTION_SHIFT,
391 #define TTBR0_BASE_ADDR_MASK 0xFFFFC000
392 #define TTBR0_RGN_NC (0 << 3)
393 #define TTBR0_RGN_WBWA (1 << 3)
394 #define TTBR0_RGN_WT (2 << 3)
395 #define TTBR0_RGN_WB (3 << 3)
396 /* TTBR0[6] is IRGN[0] and TTBR[0] is IRGN[1] */
397 #define TTBR0_IRGN_NC (0 << 0 | 0 << 6)
398 #define TTBR0_IRGN_WBWA (0 << 0 | 1 << 6)
399 #define TTBR0_IRGN_WT (1 << 0 | 0 << 6)
400 #define TTBR0_IRGN_WB (1 << 0 | 1 << 6)
404 * Register an update to the page tables, and flush the TLB
406 * \param start start address of update in page table
407 * \param stop stop address of update in page table
409 void mmu_page_table_flush(unsigned long start, unsigned long stop);
411 #endif /* __ASSEMBLY__ */
413 #define arch_align_stack(x) (x)
415 #endif /* __KERNEL__ */
417 #endif /* CONFIG_ARM64 */
421 * Change the cache settings for a region.
423 * \param start start address of memory region to change
424 * \param size size of memory region to change
425 * \param option dcache option to select
427 void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size,
428 enum dcache_option option);
430 #ifdef CONFIG_SYS_NONCACHED_MEMORY
431 void noncached_init(void);
432 phys_addr_t noncached_alloc(size_t size, size_t align);
433 #endif /* CONFIG_SYS_NONCACHED_MEMORY */
435 #endif /* __ASSEMBLY__ */