1 #ifndef __ASM_ARM_SYSTEM_H
2 #define __ASM_ARM_SYSTEM_H
4 #include <linux/compiler.h>
5 #include <asm/barriers.h>
10 * SCTLR_EL1/SCTLR_EL2/SCTLR_EL3 bits definitions
12 #define CR_M (1 << 0) /* MMU enable */
13 #define CR_A (1 << 1) /* Alignment abort enable */
14 #define CR_C (1 << 2) /* Dcache enable */
15 #define CR_SA (1 << 3) /* Stack Alignment Check Enable */
16 #define CR_I (1 << 12) /* Icache enable */
17 #define CR_WXN (1 << 19) /* Write Permision Imply XN */
18 #define CR_EE (1 << 25) /* Exception (Big) Endian */
20 #define ES_TO_AARCH64 1
21 #define ES_TO_AARCH32 0
24 * SCR_EL3 bits definitions
26 #define SCR_EL3_RW_AARCH64 (1 << 10) /* Next lower level is AArch64 */
27 #define SCR_EL3_RW_AARCH32 (0 << 10) /* Lower lowers level are AArch32 */
28 #define SCR_EL3_HCE_EN (1 << 8) /* Hypervisor Call enable */
29 #define SCR_EL3_SMD_DIS (1 << 7) /* Secure Monitor Call disable */
30 #define SCR_EL3_RES1 (3 << 4) /* Reserved, RES1 */
31 #define SCR_EL3_EA_EN (1 << 3) /* External aborts taken to EL3 */
32 #define SCR_EL3_NS_EN (1 << 0) /* EL0 and EL1 in Non-scure state */
35 * SPSR_EL3/SPSR_EL2 bits definitions
37 #define SPSR_EL_END_LE (0 << 9) /* Exception Little-endian */
38 #define SPSR_EL_DEBUG_MASK (1 << 9) /* Debug exception masked */
39 #define SPSR_EL_ASYN_MASK (1 << 8) /* Asynchronous data abort masked */
40 #define SPSR_EL_SERR_MASK (1 << 8) /* System Error exception masked */
41 #define SPSR_EL_IRQ_MASK (1 << 7) /* IRQ exception masked */
42 #define SPSR_EL_FIQ_MASK (1 << 6) /* FIQ exception masked */
43 #define SPSR_EL_T_A32 (0 << 5) /* AArch32 instruction set A32 */
44 #define SPSR_EL_M_AARCH64 (0 << 4) /* Exception taken from AArch64 */
45 #define SPSR_EL_M_AARCH32 (1 << 4) /* Exception taken from AArch32 */
46 #define SPSR_EL_M_SVC (0x3) /* Exception taken from SVC mode */
47 #define SPSR_EL_M_HYP (0xa) /* Exception taken from HYP mode */
48 #define SPSR_EL_M_EL1H (5) /* Exception taken from EL1h mode */
49 #define SPSR_EL_M_EL2H (9) /* Exception taken from EL2h mode */
52 * CPTR_EL2 bits definitions
54 #define CPTR_EL2_RES1 (3 << 12 | 0x3ff) /* Reserved, RES1 */
57 * SCTLR_EL2 bits definitions
59 #define SCTLR_EL2_RES1 (3 << 28 | 3 << 22 | 1 << 18 | 1 << 16 |\
60 1 << 11 | 3 << 4) /* Reserved, RES1 */
61 #define SCTLR_EL2_EE_LE (0 << 25) /* Exception Little-endian */
62 #define SCTLR_EL2_WXN_DIS (0 << 19) /* Write permission is not XN */
63 #define SCTLR_EL2_ICACHE_DIS (0 << 12) /* Instruction cache disabled */
64 #define SCTLR_EL2_SA_DIS (0 << 3) /* Stack Alignment Check disabled */
65 #define SCTLR_EL2_DCACHE_DIS (0 << 2) /* Data cache disabled */
66 #define SCTLR_EL2_ALIGN_DIS (0 << 1) /* Alignment check disabled */
67 #define SCTLR_EL2_MMU_DIS (0) /* MMU disabled */
70 * CNTHCTL_EL2 bits definitions
72 #define CNTHCTL_EL2_EL1PCEN_EN (1 << 1) /* Physical timer regs accessible */
73 #define CNTHCTL_EL2_EL1PCTEN_EN (1 << 0) /* Physical counter accessible */
76 * HCR_EL2 bits definitions
78 #define HCR_EL2_RW_AARCH64 (1 << 31) /* EL1 is AArch64 */
79 #define HCR_EL2_RW_AARCH32 (0 << 31) /* Lower levels are AArch32 */
80 #define HCR_EL2_HCD_DIS (1 << 29) /* Hypervisor Call disabled */
83 * CPACR_EL1 bits definitions
85 #define CPACR_EL1_FPEN_EN (3 << 20) /* SIMD and FP instruction enabled */
88 * SCTLR_EL1 bits definitions
90 #define SCTLR_EL1_RES1 (3 << 28 | 3 << 22 | 1 << 20 |\
91 1 << 11) /* Reserved, RES1 */
92 #define SCTLR_EL1_UCI_DIS (0 << 26) /* Cache instruction disabled */
93 #define SCTLR_EL1_EE_LE (0 << 25) /* Exception Little-endian */
94 #define SCTLR_EL1_WXN_DIS (0 << 19) /* Write permission is not XN */
95 #define SCTLR_EL1_NTWE_DIS (0 << 18) /* WFE instruction disabled */
96 #define SCTLR_EL1_NTWI_DIS (0 << 16) /* WFI instruction disabled */
97 #define SCTLR_EL1_UCT_DIS (0 << 15) /* CTR_EL0 access disabled */
98 #define SCTLR_EL1_DZE_DIS (0 << 14) /* DC ZVA instruction disabled */
99 #define SCTLR_EL1_ICACHE_DIS (0 << 12) /* Instruction cache disabled */
100 #define SCTLR_EL1_UMA_DIS (0 << 9) /* User Mask Access disabled */
101 #define SCTLR_EL1_SED_EN (0 << 8) /* SETEND instruction enabled */
102 #define SCTLR_EL1_ITD_EN (0 << 7) /* IT instruction enabled */
103 #define SCTLR_EL1_CP15BEN_DIS (0 << 5) /* CP15 barrier operation disabled */
104 #define SCTLR_EL1_SA0_DIS (0 << 4) /* Stack Alignment EL0 disabled */
105 #define SCTLR_EL1_SA_DIS (0 << 3) /* Stack Alignment EL1 disabled */
106 #define SCTLR_EL1_DCACHE_DIS (0 << 2) /* Data cache disabled */
107 #define SCTLR_EL1_ALIGN_DIS (0 << 1) /* Alignment check disabled */
108 #define SCTLR_EL1_MMU_DIS (0) /* MMU disabled */
114 u64 get_page_table_size(void);
115 #define PGTABLE_SIZE get_page_table_size()
117 /* 2MB granularity */
118 #define MMU_SECTION_SHIFT 21
119 #define MMU_SECTION_SIZE (1 << MMU_SECTION_SHIFT)
121 /* These constants need to be synced to the MT_ types in asm/armv8/mmu.h */
124 DCACHE_WRITETHROUGH = 3 << 2,
125 DCACHE_WRITEBACK = 4 << 2,
126 DCACHE_WRITEALLOC = 4 << 2,
131 "wfi" : : : "memory"); \
134 static inline unsigned int current_el(void)
137 asm volatile("mrs %0, CurrentEL" : "=r" (el) : : "cc");
141 static inline unsigned int get_sctlr(void)
143 unsigned int el, val;
147 asm volatile("mrs %0, sctlr_el1" : "=r" (val) : : "cc");
149 asm volatile("mrs %0, sctlr_el2" : "=r" (val) : : "cc");
151 asm volatile("mrs %0, sctlr_el3" : "=r" (val) : : "cc");
156 static inline void set_sctlr(unsigned int val)
162 asm volatile("msr sctlr_el1, %0" : : "r" (val) : "cc");
164 asm volatile("msr sctlr_el2, %0" : : "r" (val) : "cc");
166 asm volatile("msr sctlr_el3, %0" : : "r" (val) : "cc");
171 static inline unsigned long read_mpidr(void)
175 asm volatile("mrs %0, mpidr_el1" : "=r" (val));
182 void __asm_flush_dcache_all(void);
183 void __asm_invalidate_dcache_all(void);
184 void __asm_flush_dcache_range(u64 start, u64 end);
187 * __asm_invalidate_dcache_range() - Invalidate a range of virtual addresses
189 * This performance an invalidate from @start to @end - 1. Both addresses
190 * should be cache-aligned, otherwise this function will align the start
191 * address and may continue past the end address.
193 * Data in the address range is evicted from the cache and is not written back
196 * @start: Start address to invalidate
197 * @end: End address to invalidate up to (exclusive)
199 void __asm_invalidate_dcache_range(u64 start, u64 end);
200 void __asm_invalidate_tlb_all(void);
201 void __asm_invalidate_icache_all(void);
202 int __asm_invalidate_l3_dcache(void);
203 int __asm_flush_l3_dcache(void);
204 int __asm_invalidate_l3_icache(void);
205 void __asm_switch_ttbr(u64 new_ttbr);
208 * Switch from EL3 to EL2 for ARMv8
210 * @args: For loading 64-bit OS, fdt address.
211 * For loading 32-bit OS, zero.
212 * @mach_nr: For loading 64-bit OS, zero.
213 * For loading 32-bit OS, machine nr
214 * @fdt_addr: For loading 64-bit OS, zero.
215 * For loading 32-bit OS, fdt address.
216 * @arg4: Input argument.
217 * @entry_point: kernel entry point
218 * @es_flag: execution state flag, ES_TO_AARCH64 or ES_TO_AARCH32
220 void __noreturn armv8_switch_to_el2(u64 args, u64 mach_nr, u64 fdt_addr,
221 u64 arg4, u64 entry_point, u64 es_flag);
223 * Switch from EL2 to EL1 for ARMv8
225 * @args: For loading 64-bit OS, fdt address.
226 * For loading 32-bit OS, zero.
227 * @mach_nr: For loading 64-bit OS, zero.
228 * For loading 32-bit OS, machine nr
229 * @fdt_addr: For loading 64-bit OS, zero.
230 * For loading 32-bit OS, fdt address.
231 * @arg4: Input argument.
232 * @entry_point: kernel entry point
233 * @es_flag: execution state flag, ES_TO_AARCH64 or ES_TO_AARCH32
235 void armv8_switch_to_el1(u64 args, u64 mach_nr, u64 fdt_addr,
236 u64 arg4, u64 entry_point, u64 es_flag);
237 void armv8_el2_to_aarch32(u64 args, u64 mach_nr, u64 fdt_addr,
238 u64 arg4, u64 entry_point);
240 void gic_send_sgi(unsigned long sgino);
241 void wait_for_wakeup(void);
242 void protect_secure_region(void);
243 void smp_kick_all_cpus(void);
245 void flush_l3_cache(void);
246 void mmu_change_region_attr(phys_addr_t start, size_t size, u64 attrs);
249 *Issue a secure monitor call in accordance with ARM "SMC Calling convention",
252 * @args: input and output arguments
255 void smc_call(struct pt_regs *args);
257 void __noreturn psci_system_reset(void);
258 void __noreturn psci_system_reset2(u32 reset_level, u32 cookie);
259 void __noreturn psci_system_off(void);
261 #ifdef CONFIG_ARMV8_PSCI
262 extern char __secure_start[];
263 extern char __secure_end[];
264 extern char __secure_stack_start[];
265 extern char __secure_stack_end[];
267 void armv8_setup_psci(void);
268 void psci_setup_vectors(void);
269 void psci_arch_init(void);
272 #endif /* __ASSEMBLY__ */
274 #else /* CONFIG_ARM64 */
278 #define CPU_ARCH_UNKNOWN 0
279 #define CPU_ARCH_ARMv3 1
280 #define CPU_ARCH_ARMv4 2
281 #define CPU_ARCH_ARMv4T 3
282 #define CPU_ARCH_ARMv5 4
283 #define CPU_ARCH_ARMv5T 5
284 #define CPU_ARCH_ARMv5TE 6
285 #define CPU_ARCH_ARMv5TEJ 7
286 #define CPU_ARCH_ARMv6 8
287 #define CPU_ARCH_ARMv7 9
290 * CR1 bits (CP#15 CR1)
292 #define CR_M (1 << 0) /* MMU enable */
293 #define CR_A (1 << 1) /* Alignment abort enable */
294 #define CR_C (1 << 2) /* Dcache enable */
295 #define CR_W (1 << 3) /* Write buffer enable */
296 #define CR_P (1 << 4) /* 32-bit exception handler */
297 #define CR_D (1 << 5) /* 32-bit data address range */
298 #define CR_L (1 << 6) /* Implementation defined */
299 #define CR_B (1 << 7) /* Big endian */
300 #define CR_S (1 << 8) /* System MMU protection */
301 #define CR_R (1 << 9) /* ROM MMU protection */
302 #define CR_F (1 << 10) /* Implementation defined */
303 #define CR_Z (1 << 11) /* Implementation defined */
304 #define CR_I (1 << 12) /* Icache enable */
305 #define CR_V (1 << 13) /* Vectors relocated to 0xffff0000 */
306 #define CR_RR (1 << 14) /* Round Robin cache replacement */
307 #define CR_L4 (1 << 15) /* LDR pc can set T bit */
308 #define CR_DT (1 << 16)
309 #define CR_IT (1 << 18)
310 #define CR_ST (1 << 19)
311 #define CR_FI (1 << 21) /* Fast interrupt (lower latency mode) */
312 #define CR_U (1 << 22) /* Unaligned access operation */
313 #define CR_XP (1 << 23) /* Extended page tables */
314 #define CR_VE (1 << 24) /* Vectored interrupts */
315 #define CR_EE (1 << 25) /* Exception (Big) Endian */
316 #define CR_TRE (1 << 28) /* TEX remap enable */
317 #define CR_AFE (1 << 29) /* Access flag enable */
318 #define CR_TE (1 << 30) /* Thumb exception enable */
320 #if defined(CONFIG_ARMV7_LPAE) && !defined(PGTABLE_SIZE)
321 #define PGTABLE_SIZE (4096 * 5)
322 #elif !defined(PGTABLE_SIZE)
323 #define PGTABLE_SIZE (4096 * 4)
327 * This is used to ensure the compiler did actually allocate the register we
328 * asked it for some inline assembly sequences. Apparently we can't trust
329 * the compiler from one version to another so a bit of paranoia won't hurt.
330 * This string is meant to be concatenated with the inline asm string and
331 * will cause compilation to stop on mismatch.
332 * (for details, see gcc PR 15089)
334 #define __asmeq(x, y) ".ifnc " x "," y " ; .err ; .endif\n\t"
338 #ifdef CONFIG_ARMV7_LPAE
339 void switch_to_hypervisor_ret(void);
342 #define nop() __asm__ __volatile__("mov\tr0,r0\t@ nop\n\t");
344 #ifdef __ARM_ARCH_7A__
345 #define wfi() __asm__ __volatile__ ("wfi" : : : "memory")
350 static inline unsigned long get_cpsr(void)
354 asm volatile("mrs %0, cpsr" : "=r"(cpsr): );
358 static inline int is_hyp(void)
360 #ifdef CONFIG_ARMV7_LPAE
361 /* HYP mode requires LPAE ... */
362 return ((get_cpsr() & 0x1f) == 0x1a);
364 /* ... so without LPAE support we can optimize all hyp code away */
369 static inline unsigned int get_cr(void)
374 asm volatile("mrc p15, 4, %0, c1, c0, 0 @ get CR" : "=r" (val)
378 asm volatile("mrc p15, 0, %0, c1, c0, 0 @ get CR" : "=r" (val)
384 static inline void set_cr(unsigned int val)
387 asm volatile("mcr p15, 4, %0, c1, c0, 0 @ set CR" :
391 asm volatile("mcr p15, 0, %0, c1, c0, 0 @ set CR" :
397 static inline unsigned int get_dacr(void)
400 asm("mrc p15, 0, %0, c3, c0, 0 @ get DACR" : "=r" (val) : : "cc");
404 static inline void set_dacr(unsigned int val)
406 asm volatile("mcr p15, 0, %0, c3, c0, 0 @ set DACR"
407 : : "r" (val) : "cc");
411 #ifdef CONFIG_ARMV7_LPAE
412 /* Long-Descriptor Translation Table Level 1/2 Bits */
413 #define TTB_SECT_XN_MASK (1ULL << 54)
414 #define TTB_SECT_NG_MASK (1 << 11)
415 #define TTB_SECT_AF (1 << 10)
416 #define TTB_SECT_SH_MASK (3 << 8)
417 #define TTB_SECT_NS_MASK (1 << 5)
418 #define TTB_SECT_AP (1 << 6)
419 /* Note: TTB AP bits are set elsewhere */
420 #define TTB_SECT_MAIR(x) ((x & 0x7) << 2) /* Index into MAIR */
421 #define TTB_SECT (1 << 0)
422 #define TTB_PAGETABLE (3 << 0)
425 #define TTBCR_EAE (1 << 31)
426 #define TTBCR_T0SZ(x) ((x) << 0)
427 #define TTBCR_T1SZ(x) ((x) << 16)
428 #define TTBCR_USING_TTBR0 (TTBCR_T0SZ(0) | TTBCR_T1SZ(0))
429 #define TTBCR_IRGN0_NC (0 << 8)
430 #define TTBCR_IRGN0_WBWA (1 << 8)
431 #define TTBCR_IRGN0_WT (2 << 8)
432 #define TTBCR_IRGN0_WBNWA (3 << 8)
433 #define TTBCR_IRGN0_MASK (3 << 8)
434 #define TTBCR_ORGN0_NC (0 << 10)
435 #define TTBCR_ORGN0_WBWA (1 << 10)
436 #define TTBCR_ORGN0_WT (2 << 10)
437 #define TTBCR_ORGN0_WBNWA (3 << 10)
438 #define TTBCR_ORGN0_MASK (3 << 10)
439 #define TTBCR_SHARED_NON (0 << 12)
440 #define TTBCR_SHARED_OUTER (2 << 12)
441 #define TTBCR_SHARED_INNER (3 << 12)
442 #define TTBCR_EPD0 (0 << 7)
447 #define MEMORY_ATTRIBUTES ((0x00 << (0 * 8)) | (0x88 << (1 * 8)) | \
448 (0xcc << (2 * 8)) | (0xff << (3 * 8)))
450 /* options available for data cache on each page */
452 DCACHE_OFF = TTB_SECT | TTB_SECT_MAIR(0) | TTB_SECT_XN_MASK,
453 DCACHE_WRITETHROUGH = TTB_SECT | TTB_SECT_MAIR(1),
454 DCACHE_WRITEBACK = TTB_SECT | TTB_SECT_MAIR(2),
455 DCACHE_WRITEALLOC = TTB_SECT | TTB_SECT_MAIR(3),
457 #elif defined(CONFIG_CPU_V7A)
458 /* Short-Descriptor Translation Table Level 1 Bits */
459 #define TTB_SECT_NS_MASK (1 << 19)
460 #define TTB_SECT_NG_MASK (1 << 17)
461 #define TTB_SECT_S_MASK (1 << 16)
462 /* Note: TTB AP bits are set elsewhere */
463 #define TTB_SECT_AP (3 << 10)
464 #define TTB_SECT_TEX(x) ((x & 0x7) << 12)
465 #define TTB_SECT_DOMAIN(x) ((x & 0xf) << 5)
466 #define TTB_SECT_XN_MASK (1 << 4)
467 #define TTB_SECT_C_MASK (1 << 3)
468 #define TTB_SECT_B_MASK (1 << 2)
469 #define TTB_SECT (2 << 0)
471 /* options available for data cache on each page */
473 DCACHE_OFF = TTB_SECT_DOMAIN(0) | TTB_SECT_XN_MASK | TTB_SECT,
474 DCACHE_WRITETHROUGH = DCACHE_OFF | TTB_SECT_C_MASK,
475 DCACHE_WRITEBACK = DCACHE_WRITETHROUGH | TTB_SECT_B_MASK,
476 DCACHE_WRITEALLOC = DCACHE_WRITEBACK | TTB_SECT_TEX(1),
479 #define TTB_SECT_AP (3 << 10)
480 /* options available for data cache on each page */
483 DCACHE_WRITETHROUGH = 0x1a,
484 DCACHE_WRITEBACK = 0x1e,
485 DCACHE_WRITEALLOC = 0x16,
489 #if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH)
490 #define DCACHE_DEFAULT_OPTION DCACHE_WRITETHROUGH
491 #elif defined(CONFIG_SYS_ARM_CACHE_WRITEALLOC)
492 #define DCACHE_DEFAULT_OPTION DCACHE_WRITEALLOC
493 #elif defined(CONFIG_SYS_ARM_CACHE_WRITEBACK)
494 #define DCACHE_DEFAULT_OPTION DCACHE_WRITEBACK
497 /* Size of an MMU section */
499 #ifdef CONFIG_ARMV7_LPAE
500 MMU_SECTION_SHIFT = 21, /* 2MB */
502 MMU_SECTION_SHIFT = 20, /* 1MB */
504 MMU_SECTION_SIZE = 1 << MMU_SECTION_SHIFT,
507 #ifdef CONFIG_CPU_V7A
509 #define TTBR0_BASE_ADDR_MASK 0xFFFFC000
510 #define TTBR0_RGN_NC (0 << 3)
511 #define TTBR0_RGN_WBWA (1 << 3)
512 #define TTBR0_RGN_WT (2 << 3)
513 #define TTBR0_RGN_WB (3 << 3)
514 /* TTBR0[6] is IRGN[0] and TTBR[0] is IRGN[1] */
515 #define TTBR0_IRGN_NC (0 << 0 | 0 << 6)
516 #define TTBR0_IRGN_WBWA (0 << 0 | 1 << 6)
517 #define TTBR0_IRGN_WT (1 << 0 | 0 << 6)
518 #define TTBR0_IRGN_WB (1 << 0 | 1 << 6)
522 * Register an update to the page tables, and flush the TLB
524 * \param start start address of update in page table
525 * \param stop stop address of update in page table
527 void mmu_page_table_flush(unsigned long start, unsigned long stop);
529 #ifdef CONFIG_ARMV7_PSCI
530 void psci_arch_cpu_entry(void);
531 u32 psci_version(void);
532 s32 psci_features(u32 function_id, u32 psci_fid);
533 s32 psci_cpu_off(void);
534 s32 psci_cpu_on(u32 function_id, u32 target_cpu, u32 pc,
536 s32 psci_affinity_info(u32 function_id, u32 target_affinity,
537 u32 lowest_affinity_level);
538 u32 psci_migrate_info_type(void);
539 void psci_system_off(void);
540 void psci_system_reset(void);
541 s32 psci_features(u32 function_id, u32 psci_fid);
544 #endif /* __ASSEMBLY__ */
546 #define arch_align_stack(x) (x)
548 #endif /* __KERNEL__ */
550 #endif /* CONFIG_ARM64 */
554 * save_boot_params() - Save boot parameters before starting reset sequence
556 * If you provide this function it will be called immediately U-Boot starts,
557 * both for SPL and U-Boot proper.
559 * All registers are unchanged from U-Boot entry. No registers need be
562 * This is not a normal C function. There is no stack. Return by branching to
563 * save_boot_params_ret.
565 * void save_boot_params(u32 r0, u32 r1, u32 r2, u32 r3);
569 * save_boot_params_ret() - Return from save_boot_params()
571 * If you provide save_boot_params(), then you should jump back to this
572 * function when done. Try to preserve all registers.
574 * If your implementation of save_boot_params() is in C then it is acceptable
575 * to simply call save_boot_params_ret() at the end of your function. Since
576 * there is no link register set up, you cannot just exit the function. U-Boot
577 * will return to the (initialised) value of lr, and likely crash/hang.
579 * If your implementation of save_boot_params() is in assembler then you
580 * should use 'b' or 'bx' to return to save_boot_params_ret.
582 void save_boot_params_ret(void);
585 * Change the cache settings for a region.
587 * \param start start address of memory region to change
588 * \param size size of memory region to change
589 * \param option dcache option to select
591 void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size,
592 enum dcache_option option);
594 #ifdef CONFIG_SYS_NONCACHED_MEMORY
595 void noncached_init(void);
596 phys_addr_t noncached_alloc(size_t size, size_t align);
597 #endif /* CONFIG_SYS_NONCACHED_MEMORY */
599 #endif /* __ASSEMBLY__ */