2 * (C) Copyright 2004-2008 Texas Instruments, <www.ti.com>
3 * Rohit Choraria <rohitkc@ti.com>
5 * (C) Copyright 2013 Andreas Bießmann <andreas.devel@googlemail.com>
7 * SPDX-License-Identifier: GPL-2.0+
9 #ifndef __ASM_OMAP_GPMC_H
10 #define __ASM_OMAP_GPMC_H
12 #define GPMC_BUF_EMPTY 0
13 #define GPMC_BUF_FULL 1
15 /* Generic ECC Layouts */
16 /* Large Page x8 NAND device Layout */
17 #ifdef GPMC_NAND_ECC_LP_x8_LAYOUT
18 #define GPMC_NAND_HW_ECC_LAYOUT {\
20 .eccpos = {1, 2, 3, 4, 5, 6, 7, 8,\
28 /* Large Page x16 NAND device Layout */
29 #ifdef GPMC_NAND_ECC_LP_x16_LAYOUT
30 #define GPMC_NAND_HW_ECC_LAYOUT {\
32 .eccpos = {2, 3, 4, 5, 6, 7, 8, 9,\
40 /* Small Page x8 NAND device Layout */
41 #ifdef GPMC_NAND_ECC_SP_x8_LAYOUT
42 #define GPMC_NAND_HW_ECC_LAYOUT {\
51 /* Small Page x16 NAND device Layout */
52 #ifdef GPMC_NAND_ECC_SP_x16_LAYOUT
53 #define GPMC_NAND_HW_ECC_LAYOUT {\
63 /* 1-bit ECC calculation by Software, Error detection by Software */
64 OMAP_ECC_HAM1_CODE_SW = 1, /* avoid un-initialized int can be 0x0 */
65 /* 1-bit ECC calculation by GPMC, Error detection by Software */
66 /* ECC layout compatible to legacy ROMCODE. */
67 OMAP_ECC_HAM1_CODE_HW,
68 /* 4-bit ECC calculation by GPMC, Error detection by Software */
69 OMAP_ECC_BCH4_CODE_HW_DETECTION_SW,
70 /* 4-bit ECC calculation by GPMC, Error detection by ELM */
71 OMAP_ECC_BCH4_CODE_HW,
72 /* 8-bit ECC calculation by GPMC, Error detection by Software */
73 OMAP_ECC_BCH8_CODE_HW_DETECTION_SW,
74 /* 8-bit ECC calculation by GPMC, Error detection by ELM */
75 OMAP_ECC_BCH8_CODE_HW,
78 #endif /* __ASM_OMAP_GPMC_H */