Merge git://www.denx.de/git/u-boot-marvell
[oweals/u-boot.git] / arch / arm / include / asm / omap_common.h
1 /*
2  * (C) Copyright 2010
3  * Texas Instruments, <www.ti.com>
4  *
5  * Aneesh V <aneesh@ti.com>
6  *
7  * SPDX-License-Identifier:     GPL-2.0+
8  */
9 #ifndef _OMAP_COMMON_H_
10 #define _OMAP_COMMON_H_
11
12 #ifndef __ASSEMBLY__
13
14 #include <common.h>
15
16 #define NUM_SYS_CLKS    7
17
18 struct prcm_regs {
19         /* cm1.ckgen */
20         u32 cm_clksel_core;
21         u32 cm_clksel_abe;
22         u32 cm_dll_ctrl;
23         u32 cm_clkmode_dpll_core;
24         u32 cm_idlest_dpll_core;
25         u32 cm_autoidle_dpll_core;
26         u32 cm_clksel_dpll_core;
27         u32 cm_div_m2_dpll_core;
28         u32 cm_div_m3_dpll_core;
29         u32 cm_div_h11_dpll_core;
30         u32 cm_div_h12_dpll_core;
31         u32 cm_div_h13_dpll_core;
32         u32 cm_div_h14_dpll_core;
33         u32 cm_div_h21_dpll_core;
34         u32 cm_div_h24_dpll_core;
35         u32 cm_ssc_deltamstep_dpll_core;
36         u32 cm_ssc_modfreqdiv_dpll_core;
37         u32 cm_emu_override_dpll_core;
38         u32 cm_div_h22_dpllcore;
39         u32 cm_div_h23_dpll_core;
40         u32 cm_clkmode_dpll_mpu;
41         u32 cm_idlest_dpll_mpu;
42         u32 cm_autoidle_dpll_mpu;
43         u32 cm_clksel_dpll_mpu;
44         u32 cm_div_m2_dpll_mpu;
45         u32 cm_ssc_deltamstep_dpll_mpu;
46         u32 cm_ssc_modfreqdiv_dpll_mpu;
47         u32 cm_bypclk_dpll_mpu;
48         u32 cm_clkmode_dpll_iva;
49         u32 cm_idlest_dpll_iva;
50         u32 cm_autoidle_dpll_iva;
51         u32 cm_clksel_dpll_iva;
52         u32 cm_div_h11_dpll_iva;
53         u32 cm_div_h12_dpll_iva;
54         u32 cm_ssc_deltamstep_dpll_iva;
55         u32 cm_ssc_modfreqdiv_dpll_iva;
56         u32 cm_bypclk_dpll_iva;
57         u32 cm_clkmode_dpll_abe;
58         u32 cm_idlest_dpll_abe;
59         u32 cm_autoidle_dpll_abe;
60         u32 cm_clksel_dpll_abe;
61         u32 cm_div_m2_dpll_abe;
62         u32 cm_div_m3_dpll_abe;
63         u32 cm_ssc_deltamstep_dpll_abe;
64         u32 cm_ssc_modfreqdiv_dpll_abe;
65         u32 cm_clkmode_dpll_ddrphy;
66         u32 cm_idlest_dpll_ddrphy;
67         u32 cm_autoidle_dpll_ddrphy;
68         u32 cm_clksel_dpll_ddrphy;
69         u32 cm_div_m2_dpll_ddrphy;
70         u32 cm_div_h11_dpll_ddrphy;
71         u32 cm_div_h12_dpll_ddrphy;
72         u32 cm_div_h13_dpll_ddrphy;
73         u32 cm_ssc_deltamstep_dpll_ddrphy;
74         u32 cm_clkmode_dpll_dsp;
75         u32 cm_shadow_freq_config1;
76         u32 cm_clkmode_dpll_gmac;
77         u32 cm_mpu_mpu_clkctrl;
78
79         /* cm1.dsp */
80         u32 cm_dsp_clkstctrl;
81         u32 cm_dsp_dsp_clkctrl;
82
83         /* cm1.abe */
84         u32 cm1_abe_clkstctrl;
85         u32 cm1_abe_l4abe_clkctrl;
86         u32 cm1_abe_aess_clkctrl;
87         u32 cm1_abe_pdm_clkctrl;
88         u32 cm1_abe_dmic_clkctrl;
89         u32 cm1_abe_mcasp_clkctrl;
90         u32 cm1_abe_mcbsp1_clkctrl;
91         u32 cm1_abe_mcbsp2_clkctrl;
92         u32 cm1_abe_mcbsp3_clkctrl;
93         u32 cm1_abe_slimbus_clkctrl;
94         u32 cm1_abe_timer5_clkctrl;
95         u32 cm1_abe_timer6_clkctrl;
96         u32 cm1_abe_timer7_clkctrl;
97         u32 cm1_abe_timer8_clkctrl;
98         u32 cm1_abe_wdt3_clkctrl;
99
100         /* cm2.ckgen */
101         u32 cm_clksel_mpu_m3_iss_root;
102         u32 cm_clksel_usb_60mhz;
103         u32 cm_scale_fclk;
104         u32 cm_core_dvfs_perf1;
105         u32 cm_core_dvfs_perf2;
106         u32 cm_core_dvfs_perf3;
107         u32 cm_core_dvfs_perf4;
108         u32 cm_core_dvfs_current;
109         u32 cm_iva_dvfs_perf_tesla;
110         u32 cm_iva_dvfs_perf_ivahd;
111         u32 cm_iva_dvfs_perf_abe;
112         u32 cm_iva_dvfs_current;
113         u32 cm_clkmode_dpll_per;
114         u32 cm_idlest_dpll_per;
115         u32 cm_autoidle_dpll_per;
116         u32 cm_clksel_dpll_per;
117         u32 cm_div_m2_dpll_per;
118         u32 cm_div_m3_dpll_per;
119         u32 cm_div_h11_dpll_per;
120         u32 cm_div_h12_dpll_per;
121         u32 cm_div_h13_dpll_per;
122         u32 cm_div_h14_dpll_per;
123         u32 cm_ssc_deltamstep_dpll_per;
124         u32 cm_ssc_modfreqdiv_dpll_per;
125         u32 cm_emu_override_dpll_per;
126         u32 cm_clkmode_dpll_usb;
127         u32 cm_idlest_dpll_usb;
128         u32 cm_autoidle_dpll_usb;
129         u32 cm_clksel_dpll_usb;
130         u32 cm_div_m2_dpll_usb;
131         u32 cm_ssc_deltamstep_dpll_usb;
132         u32 cm_ssc_modfreqdiv_dpll_usb;
133         u32 cm_clkdcoldo_dpll_usb;
134         u32 cm_clkmode_dpll_pcie_ref;
135         u32 cm_clkmode_apll_pcie;
136         u32 cm_idlest_apll_pcie;
137         u32 cm_div_m2_apll_pcie;
138         u32 cm_clkvcoldo_apll_pcie;
139         u32 cm_clkmode_dpll_unipro;
140         u32 cm_idlest_dpll_unipro;
141         u32 cm_autoidle_dpll_unipro;
142         u32 cm_clksel_dpll_unipro;
143         u32 cm_div_m2_dpll_unipro;
144         u32 cm_ssc_deltamstep_dpll_unipro;
145         u32 cm_ssc_modfreqdiv_dpll_unipro;
146         u32 cm_coreaon_usb_phy1_core_clkctrl;
147         u32 cm_coreaon_usb_phy2_core_clkctrl;
148         u32 cm_coreaon_usb_phy3_core_clkctrl;
149         u32 cm_coreaon_l3init_60m_gfclk_clkctrl;
150
151         /* cm2.core */
152         u32 cm_coreaon_bandgap_clkctrl;
153         u32 cm_coreaon_io_srcomp_clkctrl;
154         u32 cm_l3_1_clkstctrl;
155         u32 cm_l3_1_dynamicdep;
156         u32 cm_l3_1_l3_1_clkctrl;
157         u32 cm_l3_2_clkstctrl;
158         u32 cm_l3_2_dynamicdep;
159         u32 cm_l3_2_l3_2_clkctrl;
160         u32 cm_l3_gpmc_clkctrl;
161         u32 cm_l3_2_ocmc_ram_clkctrl;
162         u32 cm_mpu_m3_clkstctrl;
163         u32 cm_mpu_m3_staticdep;
164         u32 cm_mpu_m3_dynamicdep;
165         u32 cm_mpu_m3_mpu_m3_clkctrl;
166         u32 cm_sdma_clkstctrl;
167         u32 cm_sdma_staticdep;
168         u32 cm_sdma_dynamicdep;
169         u32 cm_sdma_sdma_clkctrl;
170         u32 cm_memif_clkstctrl;
171         u32 cm_memif_dmm_clkctrl;
172         u32 cm_memif_emif_fw_clkctrl;
173         u32 cm_memif_emif_1_clkctrl;
174         u32 cm_memif_emif_2_clkctrl;
175         u32 cm_memif_dll_clkctrl;
176         u32 cm_memif_emif_h1_clkctrl;
177         u32 cm_memif_emif_h2_clkctrl;
178         u32 cm_memif_dll_h_clkctrl;
179         u32 cm_c2c_clkstctrl;
180         u32 cm_c2c_staticdep;
181         u32 cm_c2c_dynamicdep;
182         u32 cm_c2c_sad2d_clkctrl;
183         u32 cm_c2c_modem_icr_clkctrl;
184         u32 cm_c2c_sad2d_fw_clkctrl;
185         u32 cm_l4cfg_clkstctrl;
186         u32 cm_l4cfg_dynamicdep;
187         u32 cm_l4cfg_l4_cfg_clkctrl;
188         u32 cm_l4cfg_hw_sem_clkctrl;
189         u32 cm_l4cfg_mailbox_clkctrl;
190         u32 cm_l4cfg_sar_rom_clkctrl;
191         u32 cm_l3instr_clkstctrl;
192         u32 cm_l3instr_l3_3_clkctrl;
193         u32 cm_l3instr_l3_instr_clkctrl;
194         u32 cm_l3instr_intrconn_wp1_clkctrl;
195
196         /* cm2.ivahd */
197         u32 cm_ivahd_clkstctrl;
198         u32 cm_ivahd_ivahd_clkctrl;
199         u32 cm_ivahd_sl2_clkctrl;
200
201         /* cm2.cam */
202         u32 cm_cam_clkstctrl;
203         u32 cm_cam_iss_clkctrl;
204         u32 cm_cam_fdif_clkctrl;
205         u32 cm_cam_vip1_clkctrl;
206         u32 cm_cam_vip2_clkctrl;
207         u32 cm_cam_vip3_clkctrl;
208         u32 cm_cam_lvdsrx_clkctrl;
209         u32 cm_cam_csi1_clkctrl;
210         u32 cm_cam_csi2_clkctrl;
211
212         /* cm2.dss */
213         u32 cm_dss_clkstctrl;
214         u32 cm_dss_dss_clkctrl;
215
216         /* cm2.sgx */
217         u32 cm_sgx_clkstctrl;
218         u32 cm_sgx_sgx_clkctrl;
219
220         /* cm2.l3init */
221         u32 cm_l3init_clkstctrl;
222
223         /* cm2.l3init */
224         u32 cm_l3init_hsmmc1_clkctrl;
225         u32 cm_l3init_hsmmc2_clkctrl;
226         u32 cm_l3init_hsi_clkctrl;
227         u32 cm_l3init_hsusbhost_clkctrl;
228         u32 cm_l3init_hsusbotg_clkctrl;
229         u32 cm_l3init_hsusbtll_clkctrl;
230         u32 cm_l3init_p1500_clkctrl;
231         u32 cm_l3init_sata_clkctrl;
232         u32 cm_l3init_fsusb_clkctrl;
233         u32 cm_l3init_ocp2scp1_clkctrl;
234         u32 cm_l3init_ocp2scp3_clkctrl;
235         u32 cm_l3init_usb_otg_ss1_clkctrl;
236         u32 cm_l3init_usb_otg_ss2_clkctrl;
237
238         u32 prm_irqstatus_mpu;
239         u32 prm_irqstatus_mpu_2;
240
241         /* cm2.l4per */
242         u32 cm_l4per_clkstctrl;
243         u32 cm_l4per_dynamicdep;
244         u32 cm_l4per_adc_clkctrl;
245         u32 cm_l4per_gptimer10_clkctrl;
246         u32 cm_l4per_gptimer11_clkctrl;
247         u32 cm_l4per_gptimer2_clkctrl;
248         u32 cm_l4per_gptimer3_clkctrl;
249         u32 cm_l4per_gptimer4_clkctrl;
250         u32 cm_l4per_gptimer9_clkctrl;
251         u32 cm_l4per_elm_clkctrl;
252         u32 cm_l4per_gpio2_clkctrl;
253         u32 cm_l4per_gpio3_clkctrl;
254         u32 cm_l4per_gpio4_clkctrl;
255         u32 cm_l4per_gpio5_clkctrl;
256         u32 cm_l4per_gpio6_clkctrl;
257         u32 cm_l4per_hdq1w_clkctrl;
258         u32 cm_l4per_hecc1_clkctrl;
259         u32 cm_l4per_hecc2_clkctrl;
260         u32 cm_l4per_i2c1_clkctrl;
261         u32 cm_l4per_i2c2_clkctrl;
262         u32 cm_l4per_i2c3_clkctrl;
263         u32 cm_l4per_i2c4_clkctrl;
264         u32 cm_l4per_l4per_clkctrl;
265         u32 cm_l4per_mcasp2_clkctrl;
266         u32 cm_l4per_mcasp3_clkctrl;
267         u32 cm_l4per_mgate_clkctrl;
268         u32 cm_l4per_mcspi1_clkctrl;
269         u32 cm_l4per_mcspi2_clkctrl;
270         u32 cm_l4per_mcspi3_clkctrl;
271         u32 cm_l4per_mcspi4_clkctrl;
272         u32 cm_l4per_gpio7_clkctrl;
273         u32 cm_l4per_gpio8_clkctrl;
274         u32 cm_l4per_mmcsd3_clkctrl;
275         u32 cm_l4per_mmcsd4_clkctrl;
276         u32 cm_l4per_msprohg_clkctrl;
277         u32 cm_l4per_slimbus2_clkctrl;
278         u32 cm_l4per_qspi_clkctrl;
279         u32 cm_l4per_uart1_clkctrl;
280         u32 cm_l4per_uart2_clkctrl;
281         u32 cm_l4per_uart3_clkctrl;
282         u32 cm_l4per_uart4_clkctrl;
283         u32 cm_l4per_mmcsd5_clkctrl;
284         u32 cm_l4per_i2c5_clkctrl;
285         u32 cm_l4per_uart5_clkctrl;
286         u32 cm_l4per_uart6_clkctrl;
287         u32 cm_l4sec_clkstctrl;
288         u32 cm_l4sec_staticdep;
289         u32 cm_l4sec_dynamicdep;
290         u32 cm_l4sec_aes1_clkctrl;
291         u32 cm_l4sec_aes2_clkctrl;
292         u32 cm_l4sec_des3des_clkctrl;
293         u32 cm_l4sec_pkaeip29_clkctrl;
294         u32 cm_l4sec_rng_clkctrl;
295         u32 cm_l4sec_sha2md51_clkctrl;
296         u32 cm_l4sec_cryptodma_clkctrl;
297
298         /* l4 wkup regs */
299         u32 cm_abe_pll_ref_clksel;
300         u32 cm_sys_clksel;
301         u32 cm_abe_pll_sys_clksel;
302         u32 cm_wkup_clkstctrl;
303         u32 cm_wkup_l4wkup_clkctrl;
304         u32 cm_wkup_wdtimer1_clkctrl;
305         u32 cm_wkup_wdtimer2_clkctrl;
306         u32 cm_wkup_gpio1_clkctrl;
307         u32 cm_wkup_gptimer1_clkctrl;
308         u32 cm_wkup_gptimer12_clkctrl;
309         u32 cm_wkup_synctimer_clkctrl;
310         u32 cm_wkup_usim_clkctrl;
311         u32 cm_wkup_sarram_clkctrl;
312         u32 cm_wkup_keyboard_clkctrl;
313         u32 cm_wkup_rtc_clkctrl;
314         u32 cm_wkup_bandgap_clkctrl;
315         u32 cm_wkupaon_scrm_clkctrl;
316         u32 cm_wkupaon_io_srcomp_clkctrl;
317         u32 prm_rstctrl;
318         u32 prm_rstst;
319         u32 prm_rsttime;
320         u32 prm_io_pmctrl;
321         u32 prm_vc_val_bypass;
322         u32 prm_vc_cfg_i2c_mode;
323         u32 prm_vc_cfg_i2c_clk;
324         u32 prm_abbldo_mpu_setup;
325         u32 prm_abbldo_mpu_ctrl;
326         u32 prm_abbldo_mm_setup;
327         u32 prm_abbldo_mm_ctrl;
328         u32 prm_abbldo_iva_setup;
329         u32 prm_abbldo_iva_ctrl;
330         u32 prm_abbldo_eve_setup;
331         u32 prm_abbldo_eve_ctrl;
332         u32 prm_abbldo_gpu_setup;
333         u32 prm_abbldo_gpu_ctrl;
334
335         u32 cm_div_m4_dpll_core;
336         u32 cm_div_m5_dpll_core;
337         u32 cm_div_m6_dpll_core;
338         u32 cm_div_m7_dpll_core;
339         u32 cm_div_m4_dpll_iva;
340         u32 cm_div_m5_dpll_iva;
341         u32 cm_div_m4_dpll_ddrphy;
342         u32 cm_div_m5_dpll_ddrphy;
343         u32 cm_div_m6_dpll_ddrphy;
344         u32 cm_div_m4_dpll_per;
345         u32 cm_div_m5_dpll_per;
346         u32 cm_div_m6_dpll_per;
347         u32 cm_div_m7_dpll_per;
348         u32 cm_l3instr_intrconn_wp1_clkct;
349         u32 cm_l3init_usbphy_clkctrl;
350         u32 cm_l4per_mcbsp4_clkctrl;
351         u32 prm_vc_cfg_channel;
352
353         /* SCRM stuff, used by some boards */
354         u32 scrm_auxclk0;
355         u32 scrm_auxclk1;
356
357         /* GMAC Clk Ctrl */
358         u32 cm_gmac_gmac_clkctrl;
359         u32 cm_gmac_clkstctrl;
360
361         /* IPU */
362         u32 cm_ipu_clkstctrl;
363         u32 cm_ipu_i2c5_clkctrl;
364
365         /*l3main1 edma*/
366         u32 cm_l3main1_tptc1_clkctrl;
367         u32 cm_l3main1_tptc2_clkctrl;
368 };
369
370 struct omap_sys_ctrl_regs {
371         u32 control_status;
372         u32 control_core_mac_id_0_lo;
373         u32 control_core_mac_id_0_hi;
374         u32 control_core_mac_id_1_lo;
375         u32 control_core_mac_id_1_hi;
376         u32 control_phy_power_usb;
377         u32 control_core_mmr_lock1;
378         u32 control_core_mmr_lock2;
379         u32 control_core_mmr_lock3;
380         u32 control_core_mmr_lock4;
381         u32 control_core_mmr_lock5;
382         u32 control_core_control_io1;
383         u32 control_core_control_io2;
384         u32 control_id_code;
385         u32 control_std_fuse_die_id_0;
386         u32 control_std_fuse_die_id_1;
387         u32 control_std_fuse_die_id_2;
388         u32 control_std_fuse_die_id_3;
389         u32 control_std_fuse_opp_bgap;
390         u32 control_ldosram_iva_voltage_ctrl;
391         u32 control_ldosram_mpu_voltage_ctrl;
392         u32 control_ldosram_core_voltage_ctrl;
393         u32 control_usbotghs_ctrl;
394         u32 control_phy_power_sata;
395         u32 control_padconf_core_base;
396         u32 control_paconf_global;
397         u32 control_paconf_mode;
398         u32 control_smart1io_padconf_0;
399         u32 control_smart1io_padconf_1;
400         u32 control_smart1io_padconf_2;
401         u32 control_smart2io_padconf_0;
402         u32 control_smart2io_padconf_1;
403         u32 control_smart2io_padconf_2;
404         u32 control_smart3io_padconf_0;
405         u32 control_smart3io_padconf_1;
406         u32 control_pbias;
407         u32 control_i2c_0;
408         u32 control_camera_rx;
409         u32 control_hdmi_tx_phy;
410         u32 control_uniportm;
411         u32 control_dsiphy;
412         u32 control_mcbsplp;
413         u32 control_usb2phycore;
414         u32 control_hdmi_1;
415         u32 control_hsi;
416         u32 control_ddr3ch1_0;
417         u32 control_ddr3ch2_0;
418         u32 control_ddrch1_0;
419         u32 control_ddrch1_1;
420         u32 control_ddrch2_0;
421         u32 control_ddrch2_1;
422         u32 control_lpddr2ch1_0;
423         u32 control_lpddr2ch1_1;
424         u32 control_ddrio_0;
425         u32 control_ddrio_1;
426         u32 control_ddrio_2;
427         u32 control_ddr_control_ext_0;
428         u32 control_lpddr2io1_0;
429         u32 control_lpddr2io1_1;
430         u32 control_lpddr2io1_2;
431         u32 control_lpddr2io1_3;
432         u32 control_lpddr2io2_0;
433         u32 control_lpddr2io2_1;
434         u32 control_lpddr2io2_2;
435         u32 control_lpddr2io2_3;
436         u32 control_hyst_1;
437         u32 control_usbb_hsic_control;
438         u32 control_c2c;
439         u32 control_core_control_spare_rw;
440         u32 control_core_control_spare_r;
441         u32 control_core_control_spare_r_c0;
442         u32 control_srcomp_north_side;
443         u32 control_srcomp_south_side;
444         u32 control_srcomp_east_side;
445         u32 control_srcomp_west_side;
446         u32 control_srcomp_code_latch;
447         u32 control_pbiaslite;
448         u32 control_port_emif1_sdram_config;
449         u32 control_port_emif1_lpddr2_nvm_config;
450         u32 control_port_emif2_sdram_config;
451         u32 control_emif1_sdram_config_ext;
452         u32 control_emif2_sdram_config_ext;
453         u32 control_wkup_ldovbb_mpu_voltage_ctrl;
454         u32 control_wkup_ldovbb_mm_voltage_ctrl;
455         u32 control_wkup_ldovbb_iva_voltage_ctrl;
456         u32 control_wkup_ldovbb_eve_voltage_ctrl;
457         u32 control_wkup_ldovbb_gpu_voltage_ctrl;
458         u32 control_smart1nopmio_padconf_0;
459         u32 control_smart1nopmio_padconf_1;
460         u32 control_padconf_mode;
461         u32 control_xtal_oscillator;
462         u32 control_i2c_2;
463         u32 control_ckobuffer;
464         u32 control_wkup_control_spare_rw;
465         u32 control_wkup_control_spare_r;
466         u32 control_wkup_control_spare_r_c0;
467         u32 control_srcomp_east_side_wkup;
468         u32 control_efuse_1;
469         u32 control_efuse_2;
470         u32 control_efuse_3;
471         u32 control_efuse_4;
472         u32 control_efuse_5;
473         u32 control_efuse_6;
474         u32 control_efuse_7;
475         u32 control_efuse_8;
476         u32 control_efuse_9;
477         u32 control_efuse_10;
478         u32 control_efuse_11;
479         u32 control_efuse_12;
480         u32 control_efuse_13;
481         u32 control_padconf_wkup_base;
482         u32 iodelay_config_base;
483         u32 ctrl_core_sma_sw_0;
484         u32 ctrl_core_sma_sw_1;
485 };
486
487 struct dpll_params {
488         u32 m;
489         u32 n;
490         s8 m2;
491         s8 m3;
492         s8 m4_h11;
493         s8 m5_h12;
494         s8 m6_h13;
495         s8 m7_h14;
496         s8 h21;
497         s8 h22;
498         s8 h23;
499         s8 h24;
500 };
501
502 struct dpll_regs {
503         u32 cm_clkmode_dpll;
504         u32 cm_idlest_dpll;
505         u32 cm_autoidle_dpll;
506         u32 cm_clksel_dpll;
507         u32 cm_div_m2_dpll;
508         u32 cm_div_m3_dpll;
509         u32 cm_div_m4_h11_dpll;
510         u32 cm_div_m5_h12_dpll;
511         u32 cm_div_m6_h13_dpll;
512         u32 cm_div_m7_h14_dpll;
513         u32 reserved[2];
514         u32 cm_div_h21_dpll;
515         u32 cm_div_h22_dpll;
516         u32 cm_div_h23_dpll;
517         u32 cm_div_h24_dpll;
518 };
519
520 struct dplls {
521         const struct dpll_params *mpu;
522         const struct dpll_params *core;
523         const struct dpll_params *per;
524         const struct dpll_params *abe;
525         const struct dpll_params *iva;
526         const struct dpll_params *usb;
527         const struct dpll_params *ddr;
528         const struct dpll_params *gmac;
529 };
530
531 struct pmic_data {
532         u32 base_offset;
533         u32 step;
534         u32 start_code;
535         unsigned gpio;
536         int gpio_en;
537         u32 i2c_slave_addr;
538         void (*pmic_bus_init)(void);
539         int (*pmic_write)(u8 sa, u8 reg_addr, u8 reg_data);
540 };
541
542 enum {
543         OPP_LOW,
544         OPP_NOM,
545         OPP_OD,
546         OPP_HIGH,
547         NUM_OPPS,
548 };
549
550 /**
551  * struct volts_efuse_data - efuse definition for voltage
552  * @reg:        register address for efuse
553  * @reg_bits:   Number of bits in a register address, mandatory.
554  */
555 struct volts_efuse_data {
556         u32 reg[NUM_OPPS];
557         u8 reg_bits;
558 };
559
560 struct volts {
561         u32 value[NUM_OPPS];
562         u32 addr;
563         struct volts_efuse_data efuse;
564         struct pmic_data *pmic;
565
566         u32 abb_tx_done_mask;
567 };
568
569 enum {
570         VOLT_MPU,
571         VOLT_CORE,
572         VOLT_MM,
573         VOLT_GPU,
574         VOLT_EVE,
575         VOLT_IVA,
576         NUM_VOLT_RAILS,
577 };
578
579 struct vcores_data {
580         struct volts mpu;
581         struct volts core;
582         struct volts mm;
583         struct volts gpu;
584         struct volts eve;
585         struct volts iva;
586 };
587
588 extern struct prcm_regs const **prcm;
589 extern struct prcm_regs const omap5_es1_prcm;
590 extern struct prcm_regs const omap5_es2_prcm;
591 extern struct prcm_regs const omap4_prcm;
592 extern struct prcm_regs const dra7xx_prcm;
593 extern struct dplls const **dplls_data;
594 extern struct dplls dra7xx_dplls;
595 extern struct vcores_data const **omap_vcores;
596 extern const u32 sys_clk_array[8];
597 extern struct omap_sys_ctrl_regs const **ctrl;
598 extern struct omap_sys_ctrl_regs const omap4_ctrl;
599 extern struct omap_sys_ctrl_regs const omap5_ctrl;
600 extern struct omap_sys_ctrl_regs const dra7xx_ctrl;
601
602 extern struct pmic_data tps659038;
603 extern struct pmic_data lp8733;
604
605 void hw_data_init(void);
606
607 const struct dpll_params *get_mpu_dpll_params(struct dplls const *);
608 const struct dpll_params *get_core_dpll_params(struct dplls const *);
609 const struct dpll_params *get_per_dpll_params(struct dplls const *);
610 const struct dpll_params *get_iva_dpll_params(struct dplls const *);
611 const struct dpll_params *get_usb_dpll_params(struct dplls const *);
612 const struct dpll_params *get_abe_dpll_params(struct dplls const *);
613
614 void do_enable_clocks(u32 const *clk_domains,
615                       u32 const *clk_modules_hw_auto,
616                       u32 const *clk_modules_explicit_en,
617                       u8 wait_for_enable);
618
619 void do_disable_clocks(u32 const *clk_domains,
620                        u32 const *clk_modules_disable,
621                        u8 wait_for_disable);
622
623 void setup_post_dividers(u32 const base,
624                         const struct dpll_params *params);
625 u32 omap_ddr_clk(void);
626 u32 get_sys_clk_index(void);
627 void enable_basic_clocks(void);
628 void enable_basic_uboot_clocks(void);
629
630 void enable_usb_clocks(int index);
631 void disable_usb_clocks(int index);
632
633 void scale_vcores(struct vcores_data const *);
634 int get_voltrail_opp(int rail_offset);
635 u32 get_offset_code(u32 volt_offset, struct pmic_data *pmic);
636 void do_scale_vcore(u32 vcore_reg, u32 volt_mv, struct pmic_data *pmic);
637 void abb_setup(u32 fuse, u32 ldovbb, u32 setup, u32 control,
638                u32 txdone, u32 txdone_mask, u32 opp);
639 s8 abb_setup_ldovbb(u32 fuse, u32 ldovbb);
640
641 void omap_die_id_serial(void);
642 void omap_die_id_get_board_serial(struct tag_serialnr *serialnr);
643 void omap_die_id_usbethaddr(void);
644 void omap_die_id_display(void);
645
646 void recalibrate_iodelay(void);
647
648 void omap_smc1(u32 service, u32 val);
649
650 /*
651  * Low-level helper function used when performing secure ROM calls on high-
652  * security (HS) device variants by doing a specially-formed smc entry.
653  */
654 u32 omap_smc_sec(u32 service, u32 proc_id, u32 flag, u32 *params);
655 u32 omap_smc_sec_cpu1(u32 service, u32 proc_id, u32 flag, u32 *params);
656
657 void enable_edma3_clocks(void);
658 void disable_edma3_clocks(void);
659
660 void omap_die_id(unsigned int *die_id);
661
662 /* Initialize general purpose I2C(0) on the SoC */
663 void gpi2c_init(void);
664
665 /* ABB */
666 #define OMAP_ABB_NOMINAL_OPP            0
667 #define OMAP_ABB_FAST_OPP               1
668 #define OMAP_ABB_SLOW_OPP               3
669 #define OMAP_ABB_CONTROL_FAST_OPP_SEL_MASK              (0x1 << 0)
670 #define OMAP_ABB_CONTROL_SLOW_OPP_SEL_MASK              (0x1 << 1)
671 #define OMAP_ABB_CONTROL_OPP_CHANGE_MASK                (0x1 << 2)
672 #define OMAP_ABB_CONTROL_SR2_IN_TRANSITION_MASK         (0x1 << 6)
673 #define OMAP_ABB_SETUP_SR2EN_MASK                       (0x1 << 0)
674 #define OMAP_ABB_SETUP_ACTIVE_FBB_SEL_MASK              (0x1 << 2)
675 #define OMAP_ABB_SETUP_ACTIVE_RBB_SEL_MASK              (0x1 << 1)
676 #define OMAP_ABB_SETUP_SR2_WTCNT_VALUE_MASK             (0xff << 8)
677
678 static inline u32 omap_revision(void)
679 {
680         extern u32 *const omap_si_rev;
681         return *omap_si_rev;
682 }
683
684 #define OMAP44xx        0x44000000
685
686 static inline u8 is_omap44xx(void)
687 {
688         extern u32 *const omap_si_rev;
689         return (*omap_si_rev & 0xFF000000) == OMAP44xx;
690 };
691
692 #define OMAP54xx        0x54000000
693
694 static inline u8 is_omap54xx(void)
695 {
696         extern u32 *const omap_si_rev;
697         return ((*omap_si_rev & 0xFF000000) == OMAP54xx);
698 }
699
700 #define DRA7XX          0x07000000
701 #define DRA72X          0x07200000
702
703 static inline u8 is_dra7xx(void)
704 {
705         extern u32 *const omap_si_rev;
706         return ((*omap_si_rev & 0xFF000000) == DRA7XX);
707 }
708
709 static inline u8 is_dra72x(void)
710 {
711         extern u32 *const omap_si_rev;
712         return (*omap_si_rev & 0xFFF00000) == DRA72X;
713 }
714 #endif
715
716 /*
717  * silicon revisions.
718  * Moving this to common, so that most of code can be moved to common,
719  * directories.
720  */
721
722 /* omap4 */
723 #define OMAP4430_SILICON_ID_INVALID     0xFFFFFFFF
724 #define OMAP4430_ES1_0  0x44300100
725 #define OMAP4430_ES2_0  0x44300200
726 #define OMAP4430_ES2_1  0x44300210
727 #define OMAP4430_ES2_2  0x44300220
728 #define OMAP4430_ES2_3  0x44300230
729 #define OMAP4460_ES1_0  0x44600100
730 #define OMAP4460_ES1_1  0x44600110
731 #define OMAP4470_ES1_0  0x44700100
732
733 /* omap5 */
734 #define OMAP5430_SILICON_ID_INVALID     0
735 #define OMAP5430_ES1_0  0x54300100
736 #define OMAP5432_ES1_0  0x54320100
737 #define OMAP5430_ES2_0  0x54300200
738 #define OMAP5432_ES2_0  0x54320200
739
740 /* DRA7XX */
741 #define DRA752_ES1_0    0x07520100
742 #define DRA752_ES1_1    0x07520110
743 #define DRA752_ES2_0    0x07520200
744 #define DRA722_ES1_0    0x07220100
745 #define DRA722_ES2_0    0x07220200
746
747 /*
748  * silicon device type
749  * Moving to common from cpu.h, since it is shared by various omap devices
750  */
751 #define DEVICE_MASK         (BIT(8) | BIT(9) | BIT(10))
752 #define TST_DEVICE          0x0
753 #define EMU_DEVICE          0x1
754 #define HS_DEVICE           0x2
755 #define GP_DEVICE           0x3
756
757
758 /*
759  * SRAM scratch space entries
760  */
761 #define OMAP_SRAM_SCRATCH_OMAP_REV      SRAM_SCRATCH_SPACE_ADDR
762 #define OMAP_SRAM_SCRATCH_EMIF_SIZE     (SRAM_SCRATCH_SPACE_ADDR + 0x4)
763 #define OMAP_SRAM_SCRATCH_EMIF_T_NUM    (SRAM_SCRATCH_SPACE_ADDR + 0xC)
764 #define OMAP_SRAM_SCRATCH_EMIF_T_DEN    (SRAM_SCRATCH_SPACE_ADDR + 0x10)
765 #define OMAP_SRAM_SCRATCH_PRCM_PTR      (SRAM_SCRATCH_SPACE_ADDR + 0x14)
766 #define OMAP_SRAM_SCRATCH_DPLLS_PTR     (SRAM_SCRATCH_SPACE_ADDR + 0x18)
767 #define OMAP_SRAM_SCRATCH_VCORES_PTR    (SRAM_SCRATCH_SPACE_ADDR + 0x1C)
768 #define OMAP_SRAM_SCRATCH_SYS_CTRL      (SRAM_SCRATCH_SPACE_ADDR + 0x20)
769 #define OMAP_SRAM_SCRATCH_BOOT_PARAMS   (SRAM_SCRATCH_SPACE_ADDR + 0x24)
770 #define OMAP_SRAM_SCRATCH_BOARD_EEPROM_START (SRAM_SCRATCH_SPACE_ADDR + 0x28)
771 #define OMAP_SRAM_SCRATCH_BOARD_EEPROM_END (SRAM_SCRATCH_SPACE_ADDR + 0x200)
772 #define OMAP_SRAM_SCRATCH_SPACE_END     (OMAP_SRAM_SCRATCH_BOARD_EEPROM_END)
773
774 /* Boot parameters */
775 #define DEVICE_DATA_OFFSET      0x18
776 #define BOOT_MODE_OFFSET        0x8
777
778 #define CH_FLAGS_CHSETTINGS     (1 << 0)
779 #define CH_FLAGS_CHRAM          (1 << 1)
780 #define CH_FLAGS_CHFLASH        (1 << 2)
781 #define CH_FLAGS_CHMMCSD        (1 << 3)
782
783 #ifndef __ASSEMBLY__
784 u32 omap_sys_boot_device(void);
785 #endif
786
787 #endif /* _OMAP_COMMON_H_ */