2 * include/asm-arm/macro.h
4 * Copyright (C) 2009 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
6 * SPDX-License-Identifier: GPL-2.0+
9 #ifndef __ASM_ARM_MACRO_H__
10 #define __ASM_ARM_MACRO_H__
14 * These macros provide a convenient way to write 8, 16 and 32 bit data
16 * Registers r4 and r5 are used, any data in these registers are
17 * overwritten by the macros.
18 * The macros are valid for any ARM architecture, they do not implement
19 * any memory barriers so caution is recommended when using these when the
20 * caches are enabled or on a multi-core system.
23 .macro write32, addr, data
29 .macro write16, addr, data
35 .macro write8, addr, data
42 * This macro generates a loop that can be used for delays in the code.
43 * Register r4 is used, any data in this register is overwritten by the
45 * The macro is valid for any ARM architeture. The actual time spent in the
46 * loop will vary from CPU to CPU though.
49 .macro wait_timer, time
64 * Branch according to exception level
66 .macro switch_el, xreg, el3_label, el2_label, el1_label
77 * Branch if current processor is a slave,
78 * choose processor with all zero affinity value as the master.
80 .macro branch_if_slave, xreg, slave_label
82 tst \xreg, #0xff /* Test Affinity 0 */
85 tst \xreg, #0xff /* Test Affinity 1 */
88 tst \xreg, #0xff /* Test Affinity 2 */
91 tst \xreg, #0xff /* Test Affinity 3 */
96 * Branch if current processor is a master,
97 * choose processor with all zero affinity value as the master.
99 .macro branch_if_master, xreg1, xreg2, master_label
100 mrs \xreg1, mpidr_el1
101 lsr \xreg2, \xreg1, #32
102 lsl \xreg1, \xreg1, #40
103 lsr \xreg1, \xreg1, #40
104 orr \xreg1, \xreg1, \xreg2
105 cbz \xreg1, \master_label
108 .macro armv8_switch_to_el2_m, xreg1
109 /* 64bit EL2 | HCE | SMD | RES1 (Bits[5:4]) | Non-secure EL0/EL1 */
112 msr cptr_el3, xzr /* Disable coprocessor traps to EL3 */
114 msr cptr_el2, \xreg1 /* Disable coprocessor traps to EL2 */
116 /* Initialize SCTLR_EL2
118 * setting RES1 bits (29,28,23,22,18,16,11,5,4) to 1
119 * and RES0 bits (31,30,27,26,24,21,20,17,15-13,10-6) +
120 * EE,WXN,I,SA,C,A,M to 0
123 movk \xreg1, #0x30C5, lsl #16
124 msr sctlr_el2, \xreg1
126 /* Return to the EL2_SP2 mode from EL3 */
128 msr sp_el2, \xreg1 /* Migrate SP */
130 msr vbar_el2, \xreg1 /* Migrate VBAR */
132 msr spsr_el3, \xreg1 /* EL2_SP2 | D | A | I | F */
137 .macro armv8_switch_to_el1_m, xreg1, xreg2
138 /* Initialize Generic Timers */
139 mrs \xreg1, cnthctl_el2
140 orr \xreg1, \xreg1, #0x3 /* Enable EL1 access to timers */
141 msr cnthctl_el2, \xreg1
144 /* Initilize MPID/MPIDR registers */
146 mrs \xreg2, mpidr_el1
147 msr vpidr_el2, \xreg1
148 msr vmpidr_el2, \xreg2
150 /* Disable coprocessor traps */
152 msr cptr_el2, \xreg1 /* Disable coprocessor traps to EL2 */
153 msr hstr_el2, xzr /* Disable coprocessor traps to EL2 */
155 msr cpacr_el1, \xreg1 /* Enable FP/SIMD at EL1 */
157 /* Initialize HCR_EL2 */
158 mov \xreg1, #(1 << 31) /* 64bit EL1 */
159 orr \xreg1, \xreg1, #(1 << 29) /* Disable HVC */
162 /* SCTLR_EL1 initialization
164 * setting RES1 bits (29,28,23,22,20,11) to 1
165 * and RES0 bits (31,30,27,21,17,13,10,6) +
166 * UCI,EE,EOE,WXN,nTWE,nTWI,UCT,DZE,I,UMA,SED,ITD,
167 * CP15BEN,SA0,SA,C,A,M to 0
170 movk \xreg1, #0x30d0, lsl #16
171 msr sctlr_el1, \xreg1
173 /* Return to the EL1_SP1 mode from EL2 */
175 msr sp_el1, \xreg1 /* Migrate SP */
177 msr vbar_el1, \xreg1 /* Migrate VBAR */
179 msr spsr_el2, \xreg1 /* EL1_SP1 | D | A | I | F */
184 #if defined(CONFIG_GICV3)
185 .macro gic_wait_for_interrupt_m xreg1
187 mrs \xreg1, ICC_IAR1_EL1
188 msr ICC_EOIR1_EL1, \xreg1
191 #elif defined(CONFIG_GICV2)
192 .macro gic_wait_for_interrupt_m xreg1, wreg2
194 ldr \wreg2, [\xreg1, GICC_AIAR]
195 str \wreg2, [\xreg1, GICC_AEOIR]
196 and \wreg2, \wreg2, #0x3ff
201 #endif /* CONFIG_ARM64 */
203 #endif /* __ASSEMBLY__ */
204 #endif /* __ASM_ARM_MACRO_H__ */