2 * include/asm-arm/macro.h
4 * Copyright (C) 2009 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
6 * SPDX-License-Identifier: GPL-2.0+
9 #ifndef __ASM_ARM_MACRO_H__
10 #define __ASM_ARM_MACRO_H__
14 * These macros provide a convenient way to write 8, 16 and 32 bit data
16 * Registers r4 and r5 are used, any data in these registers are
17 * overwritten by the macros.
18 * The macros are valid for any ARM architecture, they do not implement
19 * any memory barriers so caution is recommended when using these when the
20 * caches are enabled or on a multi-core system.
23 .macro write32, addr, data
29 .macro write16, addr, data
35 .macro write8, addr, data
42 * This macro generates a loop that can be used for delays in the code.
43 * Register r4 is used, any data in this register is overwritten by the
45 * The macro is valid for any ARM architeture. The actual time spent in the
46 * loop will vary from CPU to CPU though.
49 .macro wait_timer, time
64 * Branch according to exception level
66 .macro switch_el, xreg, el3_label, el2_label, el1_label
77 * Branch if current processor is a Cortex-A57 core.
79 .macro branch_if_a57_core, xreg, a57_label
82 and \xreg, \xreg, #0x00000FFF
83 cmp \xreg, #0xD07 /* Cortex-A57 MPCore processor. */
88 * Branch if current processor is a Cortex-A53 core.
90 .macro branch_if_a53_core, xreg, a53_label
93 and \xreg, \xreg, #0x00000FFF
94 cmp \xreg, #0xD03 /* Cortex-A53 MPCore processor. */
99 * Branch if current processor is a slave,
100 * choose processor with all zero affinity value as the master.
102 .macro branch_if_slave, xreg, slave_label
104 tst \xreg, #0xff /* Test Affinity 0 */
107 tst \xreg, #0xff /* Test Affinity 1 */
110 tst \xreg, #0xff /* Test Affinity 2 */
112 lsr \xreg, \xreg, #16
113 tst \xreg, #0xff /* Test Affinity 3 */
118 * Branch if current processor is a master,
119 * choose processor with all zero affinity value as the master.
121 .macro branch_if_master, xreg1, xreg2, master_label
122 mrs \xreg1, mpidr_el1
123 lsr \xreg2, \xreg1, #32
124 lsl \xreg1, \xreg1, #40
125 lsr \xreg1, \xreg1, #40
126 orr \xreg1, \xreg1, \xreg2
127 cbz \xreg1, \master_label
130 .macro armv8_switch_to_el2_m, xreg1
131 /* 64bit EL2 | HCE | SMD | RES1 (Bits[5:4]) | Non-secure EL0/EL1 */
134 msr cptr_el3, xzr /* Disable coprocessor traps to EL3 */
136 msr cptr_el2, \xreg1 /* Disable coprocessor traps to EL2 */
138 /* Initialize SCTLR_EL2
140 * setting RES1 bits (29,28,23,22,18,16,11,5,4) to 1
141 * and RES0 bits (31,30,27,26,24,21,20,17,15-13,10-6) +
142 * EE,WXN,I,SA,C,A,M to 0
145 movk \xreg1, #0x30C5, lsl #16
146 msr sctlr_el2, \xreg1
148 /* Return to the EL2_SP2 mode from EL3 */
150 msr sp_el2, \xreg1 /* Migrate SP */
152 msr vbar_el2, \xreg1 /* Migrate VBAR */
154 msr spsr_el3, \xreg1 /* EL2_SP2 | D | A | I | F */
159 .macro armv8_switch_to_el1_m, xreg1, xreg2
160 /* Initialize Generic Timers */
161 mrs \xreg1, cnthctl_el2
162 orr \xreg1, \xreg1, #0x3 /* Enable EL1 access to timers */
163 msr cnthctl_el2, \xreg1
166 /* Initilize MPID/MPIDR registers */
168 mrs \xreg2, mpidr_el1
169 msr vpidr_el2, \xreg1
170 msr vmpidr_el2, \xreg2
172 /* Disable coprocessor traps */
174 msr cptr_el2, \xreg1 /* Disable coprocessor traps to EL2 */
175 msr hstr_el2, xzr /* Disable coprocessor traps to EL2 */
177 msr cpacr_el1, \xreg1 /* Enable FP/SIMD at EL1 */
179 /* Initialize HCR_EL2 */
180 mov \xreg1, #(1 << 31) /* 64bit EL1 */
181 orr \xreg1, \xreg1, #(1 << 29) /* Disable HVC */
184 /* SCTLR_EL1 initialization
186 * setting RES1 bits (29,28,23,22,20,11) to 1
187 * and RES0 bits (31,30,27,21,17,13,10,6) +
188 * UCI,EE,EOE,WXN,nTWE,nTWI,UCT,DZE,I,UMA,SED,ITD,
189 * CP15BEN,SA0,SA,C,A,M to 0
192 movk \xreg1, #0x30d0, lsl #16
193 msr sctlr_el1, \xreg1
195 /* Return to the EL1_SP1 mode from EL2 */
197 msr sp_el1, \xreg1 /* Migrate SP */
199 msr vbar_el1, \xreg1 /* Migrate VBAR */
201 msr spsr_el2, \xreg1 /* EL1_SP1 | D | A | I | F */
206 #if defined(CONFIG_GICV3)
207 .macro gic_wait_for_interrupt_m xreg1
209 mrs \xreg1, ICC_IAR1_EL1
210 msr ICC_EOIR1_EL1, \xreg1
213 #elif defined(CONFIG_GICV2)
214 .macro gic_wait_for_interrupt_m xreg1, wreg2
216 ldr \wreg2, [\xreg1, GICC_AIAR]
217 str \wreg2, [\xreg1, GICC_AEOIR]
218 and \wreg2, \wreg2, #0x3ff
223 #endif /* CONFIG_ARM64 */
225 #endif /* __ASSEMBLY__ */
226 #endif /* __ASM_ARM_MACRO_H__ */