rockchip: pinctrl: rk3368: move IOMUX bit-definitions to pinctrl driver
[oweals/u-boot.git] / arch / arm / include / asm / mach-imx / regs-apbh.h
1 /*
2  * Freescale i.MX28 APBH Register Definitions
3  *
4  * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
5  * on behalf of DENX Software Engineering GmbH
6  *
7  * Based on code from LTIB:
8  * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved.
9  *
10  * SPDX-License-Identifier:     GPL-2.0+
11  */
12
13 #ifndef __REGS_APBH_H__
14 #define __REGS_APBH_H__
15
16 #include <asm/mach-imx/regs-common.h>
17
18 #ifndef __ASSEMBLY__
19
20 #if defined(CONFIG_MX23)
21 struct mxs_apbh_regs {
22         mxs_reg_32(hw_apbh_ctrl0)
23         mxs_reg_32(hw_apbh_ctrl1)
24         mxs_reg_32(hw_apbh_ctrl2)
25         mxs_reg_32(hw_apbh_channel_ctrl)
26
27         union {
28         struct {
29                 mxs_reg_32(hw_apbh_ch_curcmdar)
30                 mxs_reg_32(hw_apbh_ch_nxtcmdar)
31                 mxs_reg_32(hw_apbh_ch_cmd)
32                 mxs_reg_32(hw_apbh_ch_bar)
33                 mxs_reg_32(hw_apbh_ch_sema)
34                 mxs_reg_32(hw_apbh_ch_debug1)
35                 mxs_reg_32(hw_apbh_ch_debug2)
36         } ch[8];
37         struct {
38                 mxs_reg_32(hw_apbh_ch0_curcmdar)
39                 mxs_reg_32(hw_apbh_ch0_nxtcmdar)
40                 mxs_reg_32(hw_apbh_ch0_cmd)
41                 mxs_reg_32(hw_apbh_ch0_bar)
42                 mxs_reg_32(hw_apbh_ch0_sema)
43                 mxs_reg_32(hw_apbh_ch0_debug1)
44                 mxs_reg_32(hw_apbh_ch0_debug2)
45                 mxs_reg_32(hw_apbh_ch1_curcmdar)
46                 mxs_reg_32(hw_apbh_ch1_nxtcmdar)
47                 mxs_reg_32(hw_apbh_ch1_cmd)
48                 mxs_reg_32(hw_apbh_ch1_bar)
49                 mxs_reg_32(hw_apbh_ch1_sema)
50                 mxs_reg_32(hw_apbh_ch1_debug1)
51                 mxs_reg_32(hw_apbh_ch1_debug2)
52                 mxs_reg_32(hw_apbh_ch2_curcmdar)
53                 mxs_reg_32(hw_apbh_ch2_nxtcmdar)
54                 mxs_reg_32(hw_apbh_ch2_cmd)
55                 mxs_reg_32(hw_apbh_ch2_bar)
56                 mxs_reg_32(hw_apbh_ch2_sema)
57                 mxs_reg_32(hw_apbh_ch2_debug1)
58                 mxs_reg_32(hw_apbh_ch2_debug2)
59                 mxs_reg_32(hw_apbh_ch3_curcmdar)
60                 mxs_reg_32(hw_apbh_ch3_nxtcmdar)
61                 mxs_reg_32(hw_apbh_ch3_cmd)
62                 mxs_reg_32(hw_apbh_ch3_bar)
63                 mxs_reg_32(hw_apbh_ch3_sema)
64                 mxs_reg_32(hw_apbh_ch3_debug1)
65                 mxs_reg_32(hw_apbh_ch3_debug2)
66                 mxs_reg_32(hw_apbh_ch4_curcmdar)
67                 mxs_reg_32(hw_apbh_ch4_nxtcmdar)
68                 mxs_reg_32(hw_apbh_ch4_cmd)
69                 mxs_reg_32(hw_apbh_ch4_bar)
70                 mxs_reg_32(hw_apbh_ch4_sema)
71                 mxs_reg_32(hw_apbh_ch4_debug1)
72                 mxs_reg_32(hw_apbh_ch4_debug2)
73                 mxs_reg_32(hw_apbh_ch5_curcmdar)
74                 mxs_reg_32(hw_apbh_ch5_nxtcmdar)
75                 mxs_reg_32(hw_apbh_ch5_cmd)
76                 mxs_reg_32(hw_apbh_ch5_bar)
77                 mxs_reg_32(hw_apbh_ch5_sema)
78                 mxs_reg_32(hw_apbh_ch5_debug1)
79                 mxs_reg_32(hw_apbh_ch5_debug2)
80                 mxs_reg_32(hw_apbh_ch6_curcmdar)
81                 mxs_reg_32(hw_apbh_ch6_nxtcmdar)
82                 mxs_reg_32(hw_apbh_ch6_cmd)
83                 mxs_reg_32(hw_apbh_ch6_bar)
84                 mxs_reg_32(hw_apbh_ch6_sema)
85                 mxs_reg_32(hw_apbh_ch6_debug1)
86                 mxs_reg_32(hw_apbh_ch6_debug2)
87                 mxs_reg_32(hw_apbh_ch7_curcmdar)
88                 mxs_reg_32(hw_apbh_ch7_nxtcmdar)
89                 mxs_reg_32(hw_apbh_ch7_cmd)
90                 mxs_reg_32(hw_apbh_ch7_bar)
91                 mxs_reg_32(hw_apbh_ch7_sema)
92                 mxs_reg_32(hw_apbh_ch7_debug1)
93                 mxs_reg_32(hw_apbh_ch7_debug2)
94         };
95         };
96         mxs_reg_32(hw_apbh_version)
97 };
98
99 #elif (defined(CONFIG_MX28) || defined(CONFIG_MX6) || defined(CONFIG_MX7))
100 struct mxs_apbh_regs {
101         mxs_reg_32(hw_apbh_ctrl0)
102         mxs_reg_32(hw_apbh_ctrl1)
103         mxs_reg_32(hw_apbh_ctrl2)
104         mxs_reg_32(hw_apbh_channel_ctrl)
105         mxs_reg_32(hw_apbh_devsel)
106         mxs_reg_32(hw_apbh_dma_burst_size)
107         mxs_reg_32(hw_apbh_debug)
108
109         uint32_t        reserved[36];
110
111         union {
112         struct {
113                 mxs_reg_32(hw_apbh_ch_curcmdar)
114                 mxs_reg_32(hw_apbh_ch_nxtcmdar)
115                 mxs_reg_32(hw_apbh_ch_cmd)
116                 mxs_reg_32(hw_apbh_ch_bar)
117                 mxs_reg_32(hw_apbh_ch_sema)
118                 mxs_reg_32(hw_apbh_ch_debug1)
119                 mxs_reg_32(hw_apbh_ch_debug2)
120         } ch[16];
121         struct {
122                 mxs_reg_32(hw_apbh_ch0_curcmdar)
123                 mxs_reg_32(hw_apbh_ch0_nxtcmdar)
124                 mxs_reg_32(hw_apbh_ch0_cmd)
125                 mxs_reg_32(hw_apbh_ch0_bar)
126                 mxs_reg_32(hw_apbh_ch0_sema)
127                 mxs_reg_32(hw_apbh_ch0_debug1)
128                 mxs_reg_32(hw_apbh_ch0_debug2)
129                 mxs_reg_32(hw_apbh_ch1_curcmdar)
130                 mxs_reg_32(hw_apbh_ch1_nxtcmdar)
131                 mxs_reg_32(hw_apbh_ch1_cmd)
132                 mxs_reg_32(hw_apbh_ch1_bar)
133                 mxs_reg_32(hw_apbh_ch1_sema)
134                 mxs_reg_32(hw_apbh_ch1_debug1)
135                 mxs_reg_32(hw_apbh_ch1_debug2)
136                 mxs_reg_32(hw_apbh_ch2_curcmdar)
137                 mxs_reg_32(hw_apbh_ch2_nxtcmdar)
138                 mxs_reg_32(hw_apbh_ch2_cmd)
139                 mxs_reg_32(hw_apbh_ch2_bar)
140                 mxs_reg_32(hw_apbh_ch2_sema)
141                 mxs_reg_32(hw_apbh_ch2_debug1)
142                 mxs_reg_32(hw_apbh_ch2_debug2)
143                 mxs_reg_32(hw_apbh_ch3_curcmdar)
144                 mxs_reg_32(hw_apbh_ch3_nxtcmdar)
145                 mxs_reg_32(hw_apbh_ch3_cmd)
146                 mxs_reg_32(hw_apbh_ch3_bar)
147                 mxs_reg_32(hw_apbh_ch3_sema)
148                 mxs_reg_32(hw_apbh_ch3_debug1)
149                 mxs_reg_32(hw_apbh_ch3_debug2)
150                 mxs_reg_32(hw_apbh_ch4_curcmdar)
151                 mxs_reg_32(hw_apbh_ch4_nxtcmdar)
152                 mxs_reg_32(hw_apbh_ch4_cmd)
153                 mxs_reg_32(hw_apbh_ch4_bar)
154                 mxs_reg_32(hw_apbh_ch4_sema)
155                 mxs_reg_32(hw_apbh_ch4_debug1)
156                 mxs_reg_32(hw_apbh_ch4_debug2)
157                 mxs_reg_32(hw_apbh_ch5_curcmdar)
158                 mxs_reg_32(hw_apbh_ch5_nxtcmdar)
159                 mxs_reg_32(hw_apbh_ch5_cmd)
160                 mxs_reg_32(hw_apbh_ch5_bar)
161                 mxs_reg_32(hw_apbh_ch5_sema)
162                 mxs_reg_32(hw_apbh_ch5_debug1)
163                 mxs_reg_32(hw_apbh_ch5_debug2)
164                 mxs_reg_32(hw_apbh_ch6_curcmdar)
165                 mxs_reg_32(hw_apbh_ch6_nxtcmdar)
166                 mxs_reg_32(hw_apbh_ch6_cmd)
167                 mxs_reg_32(hw_apbh_ch6_bar)
168                 mxs_reg_32(hw_apbh_ch6_sema)
169                 mxs_reg_32(hw_apbh_ch6_debug1)
170                 mxs_reg_32(hw_apbh_ch6_debug2)
171                 mxs_reg_32(hw_apbh_ch7_curcmdar)
172                 mxs_reg_32(hw_apbh_ch7_nxtcmdar)
173                 mxs_reg_32(hw_apbh_ch7_cmd)
174                 mxs_reg_32(hw_apbh_ch7_bar)
175                 mxs_reg_32(hw_apbh_ch7_sema)
176                 mxs_reg_32(hw_apbh_ch7_debug1)
177                 mxs_reg_32(hw_apbh_ch7_debug2)
178                 mxs_reg_32(hw_apbh_ch8_curcmdar)
179                 mxs_reg_32(hw_apbh_ch8_nxtcmdar)
180                 mxs_reg_32(hw_apbh_ch8_cmd)
181                 mxs_reg_32(hw_apbh_ch8_bar)
182                 mxs_reg_32(hw_apbh_ch8_sema)
183                 mxs_reg_32(hw_apbh_ch8_debug1)
184                 mxs_reg_32(hw_apbh_ch8_debug2)
185                 mxs_reg_32(hw_apbh_ch9_curcmdar)
186                 mxs_reg_32(hw_apbh_ch9_nxtcmdar)
187                 mxs_reg_32(hw_apbh_ch9_cmd)
188                 mxs_reg_32(hw_apbh_ch9_bar)
189                 mxs_reg_32(hw_apbh_ch9_sema)
190                 mxs_reg_32(hw_apbh_ch9_debug1)
191                 mxs_reg_32(hw_apbh_ch9_debug2)
192                 mxs_reg_32(hw_apbh_ch10_curcmdar)
193                 mxs_reg_32(hw_apbh_ch10_nxtcmdar)
194                 mxs_reg_32(hw_apbh_ch10_cmd)
195                 mxs_reg_32(hw_apbh_ch10_bar)
196                 mxs_reg_32(hw_apbh_ch10_sema)
197                 mxs_reg_32(hw_apbh_ch10_debug1)
198                 mxs_reg_32(hw_apbh_ch10_debug2)
199                 mxs_reg_32(hw_apbh_ch11_curcmdar)
200                 mxs_reg_32(hw_apbh_ch11_nxtcmdar)
201                 mxs_reg_32(hw_apbh_ch11_cmd)
202                 mxs_reg_32(hw_apbh_ch11_bar)
203                 mxs_reg_32(hw_apbh_ch11_sema)
204                 mxs_reg_32(hw_apbh_ch11_debug1)
205                 mxs_reg_32(hw_apbh_ch11_debug2)
206                 mxs_reg_32(hw_apbh_ch12_curcmdar)
207                 mxs_reg_32(hw_apbh_ch12_nxtcmdar)
208                 mxs_reg_32(hw_apbh_ch12_cmd)
209                 mxs_reg_32(hw_apbh_ch12_bar)
210                 mxs_reg_32(hw_apbh_ch12_sema)
211                 mxs_reg_32(hw_apbh_ch12_debug1)
212                 mxs_reg_32(hw_apbh_ch12_debug2)
213                 mxs_reg_32(hw_apbh_ch13_curcmdar)
214                 mxs_reg_32(hw_apbh_ch13_nxtcmdar)
215                 mxs_reg_32(hw_apbh_ch13_cmd)
216                 mxs_reg_32(hw_apbh_ch13_bar)
217                 mxs_reg_32(hw_apbh_ch13_sema)
218                 mxs_reg_32(hw_apbh_ch13_debug1)
219                 mxs_reg_32(hw_apbh_ch13_debug2)
220                 mxs_reg_32(hw_apbh_ch14_curcmdar)
221                 mxs_reg_32(hw_apbh_ch14_nxtcmdar)
222                 mxs_reg_32(hw_apbh_ch14_cmd)
223                 mxs_reg_32(hw_apbh_ch14_bar)
224                 mxs_reg_32(hw_apbh_ch14_sema)
225                 mxs_reg_32(hw_apbh_ch14_debug1)
226                 mxs_reg_32(hw_apbh_ch14_debug2)
227                 mxs_reg_32(hw_apbh_ch15_curcmdar)
228                 mxs_reg_32(hw_apbh_ch15_nxtcmdar)
229                 mxs_reg_32(hw_apbh_ch15_cmd)
230                 mxs_reg_32(hw_apbh_ch15_bar)
231                 mxs_reg_32(hw_apbh_ch15_sema)
232                 mxs_reg_32(hw_apbh_ch15_debug1)
233                 mxs_reg_32(hw_apbh_ch15_debug2)
234         };
235         };
236         mxs_reg_32(hw_apbh_version)
237 };
238 #endif
239
240 #endif
241
242 #define APBH_CTRL0_SFTRST                               (1 << 31)
243 #define APBH_CTRL0_CLKGATE                              (1 << 30)
244 #define APBH_CTRL0_AHB_BURST8_EN                        (1 << 29)
245 #define APBH_CTRL0_APB_BURST_EN                         (1 << 28)
246 #if defined(CONFIG_MX23)
247 #define APBH_CTRL0_RSVD0_MASK                           (0xf << 24)
248 #define APBH_CTRL0_RSVD0_OFFSET                         24
249 #define APBH_CTRL0_RESET_CHANNEL_MASK                   (0xff << 16)
250 #define APBH_CTRL0_RESET_CHANNEL_OFFSET                 16
251 #define APBH_CTRL0_CLKGATE_CHANNEL_MASK                 (0xff << 8)
252 #define APBH_CTRL0_CLKGATE_CHANNEL_OFFSET               8
253 #define APBH_CTRL0_CLKGATE_CHANNEL_SSP0                 0x02
254 #define APBH_CTRL0_CLKGATE_CHANNEL_SSP1                 0x04
255 #define APBH_CTRL0_CLKGATE_CHANNEL_NAND0                0x10
256 #define APBH_CTRL0_CLKGATE_CHANNEL_NAND1                0x20
257 #define APBH_CTRL0_CLKGATE_CHANNEL_NAND2                0x40
258 #define APBH_CTRL0_CLKGATE_CHANNEL_NAND3                0x80
259 #elif defined(CONFIG_MX28)
260 #define APBH_CTRL0_RSVD0_MASK                           (0xfff << 16)
261 #define APBH_CTRL0_RSVD0_OFFSET                         16
262 #define APBH_CTRL0_CLKGATE_CHANNEL_MASK                 0xffff
263 #define APBH_CTRL0_CLKGATE_CHANNEL_OFFSET               0
264 #define APBH_CTRL0_CLKGATE_CHANNEL_SSP0                 0x0001
265 #define APBH_CTRL0_CLKGATE_CHANNEL_SSP1                 0x0002
266 #define APBH_CTRL0_CLKGATE_CHANNEL_SSP2                 0x0004
267 #define APBH_CTRL0_CLKGATE_CHANNEL_SSP3                 0x0008
268 #define APBH_CTRL0_CLKGATE_CHANNEL_NAND0                0x0010
269 #define APBH_CTRL0_CLKGATE_CHANNEL_NAND1                0x0020
270 #define APBH_CTRL0_CLKGATE_CHANNEL_NAND2                0x0040
271 #define APBH_CTRL0_CLKGATE_CHANNEL_NAND3                0x0080
272 #define APBH_CTRL0_CLKGATE_CHANNEL_NAND4                0x0100
273 #define APBH_CTRL0_CLKGATE_CHANNEL_NAND5                0x0200
274 #define APBH_CTRL0_CLKGATE_CHANNEL_NAND6                0x0400
275 #define APBH_CTRL0_CLKGATE_CHANNEL_NAND7                0x0800
276 #define APBH_CTRL0_CLKGATE_CHANNEL_HSADC                0x1000
277 #define APBH_CTRL0_CLKGATE_CHANNEL_LCDIF                0x2000
278 #elif (defined(CONFIG_MX6) || defined(CONFIG_MX7))
279 #define APBH_CTRL0_CLKGATE_CHANNEL_OFFSET               0
280 #define APBH_CTRL0_CLKGATE_CHANNEL_NAND0                0x0001
281 #define APBH_CTRL0_CLKGATE_CHANNEL_NAND1                0x0002
282 #define APBH_CTRL0_CLKGATE_CHANNEL_NAND2                0x0004
283 #define APBH_CTRL0_CLKGATE_CHANNEL_NAND3                0x0008
284 #define APBH_CTRL0_CLKGATE_CHANNEL_NAND4                0x0010
285 #define APBH_CTRL0_CLKGATE_CHANNEL_NAND5                0x0020
286 #define APBH_CTRL0_CLKGATE_CHANNEL_NAND6                0x0040
287 #define APBH_CTRL0_CLKGATE_CHANNEL_NAND7                0x0080
288 #define APBH_CTRL0_CLKGATE_CHANNEL_SSP                  0x0100
289 #endif
290
291 #define APBH_CTRL1_CH15_CMDCMPLT_IRQ_EN                 (1 << 31)
292 #define APBH_CTRL1_CH14_CMDCMPLT_IRQ_EN                 (1 << 30)
293 #define APBH_CTRL1_CH13_CMDCMPLT_IRQ_EN                 (1 << 29)
294 #define APBH_CTRL1_CH12_CMDCMPLT_IRQ_EN                 (1 << 28)
295 #define APBH_CTRL1_CH11_CMDCMPLT_IRQ_EN                 (1 << 27)
296 #define APBH_CTRL1_CH10_CMDCMPLT_IRQ_EN                 (1 << 26)
297 #define APBH_CTRL1_CH9_CMDCMPLT_IRQ_EN                  (1 << 25)
298 #define APBH_CTRL1_CH8_CMDCMPLT_IRQ_EN                  (1 << 24)
299 #define APBH_CTRL1_CH7_CMDCMPLT_IRQ_EN                  (1 << 23)
300 #define APBH_CTRL1_CH6_CMDCMPLT_IRQ_EN                  (1 << 22)
301 #define APBH_CTRL1_CH5_CMDCMPLT_IRQ_EN                  (1 << 21)
302 #define APBH_CTRL1_CH4_CMDCMPLT_IRQ_EN                  (1 << 20)
303 #define APBH_CTRL1_CH3_CMDCMPLT_IRQ_EN                  (1 << 19)
304 #define APBH_CTRL1_CH2_CMDCMPLT_IRQ_EN                  (1 << 18)
305 #define APBH_CTRL1_CH1_CMDCMPLT_IRQ_EN                  (1 << 17)
306 #define APBH_CTRL1_CH0_CMDCMPLT_IRQ_EN                  (1 << 16)
307 #define APBH_CTRL1_CH_CMDCMPLT_IRQ_EN_OFFSET            16
308 #define APBH_CTRL1_CH_CMDCMPLT_IRQ_EN_MASK              (0xffff << 16)
309 #define APBH_CTRL1_CH15_CMDCMPLT_IRQ                    (1 << 15)
310 #define APBH_CTRL1_CH14_CMDCMPLT_IRQ                    (1 << 14)
311 #define APBH_CTRL1_CH13_CMDCMPLT_IRQ                    (1 << 13)
312 #define APBH_CTRL1_CH12_CMDCMPLT_IRQ                    (1 << 12)
313 #define APBH_CTRL1_CH11_CMDCMPLT_IRQ                    (1 << 11)
314 #define APBH_CTRL1_CH10_CMDCMPLT_IRQ                    (1 << 10)
315 #define APBH_CTRL1_CH9_CMDCMPLT_IRQ                     (1 << 9)
316 #define APBH_CTRL1_CH8_CMDCMPLT_IRQ                     (1 << 8)
317 #define APBH_CTRL1_CH7_CMDCMPLT_IRQ                     (1 << 7)
318 #define APBH_CTRL1_CH6_CMDCMPLT_IRQ                     (1 << 6)
319 #define APBH_CTRL1_CH5_CMDCMPLT_IRQ                     (1 << 5)
320 #define APBH_CTRL1_CH4_CMDCMPLT_IRQ                     (1 << 4)
321 #define APBH_CTRL1_CH3_CMDCMPLT_IRQ                     (1 << 3)
322 #define APBH_CTRL1_CH2_CMDCMPLT_IRQ                     (1 << 2)
323 #define APBH_CTRL1_CH1_CMDCMPLT_IRQ                     (1 << 1)
324 #define APBH_CTRL1_CH0_CMDCMPLT_IRQ                     (1 << 0)
325
326 #define APBH_CTRL2_CH15_ERROR_STATUS                    (1 << 31)
327 #define APBH_CTRL2_CH14_ERROR_STATUS                    (1 << 30)
328 #define APBH_CTRL2_CH13_ERROR_STATUS                    (1 << 29)
329 #define APBH_CTRL2_CH12_ERROR_STATUS                    (1 << 28)
330 #define APBH_CTRL2_CH11_ERROR_STATUS                    (1 << 27)
331 #define APBH_CTRL2_CH10_ERROR_STATUS                    (1 << 26)
332 #define APBH_CTRL2_CH9_ERROR_STATUS                     (1 << 25)
333 #define APBH_CTRL2_CH8_ERROR_STATUS                     (1 << 24)
334 #define APBH_CTRL2_CH7_ERROR_STATUS                     (1 << 23)
335 #define APBH_CTRL2_CH6_ERROR_STATUS                     (1 << 22)
336 #define APBH_CTRL2_CH5_ERROR_STATUS                     (1 << 21)
337 #define APBH_CTRL2_CH4_ERROR_STATUS                     (1 << 20)
338 #define APBH_CTRL2_CH3_ERROR_STATUS                     (1 << 19)
339 #define APBH_CTRL2_CH2_ERROR_STATUS                     (1 << 18)
340 #define APBH_CTRL2_CH1_ERROR_STATUS                     (1 << 17)
341 #define APBH_CTRL2_CH0_ERROR_STATUS                     (1 << 16)
342 #define APBH_CTRL2_CH15_ERROR_IRQ                       (1 << 15)
343 #define APBH_CTRL2_CH14_ERROR_IRQ                       (1 << 14)
344 #define APBH_CTRL2_CH13_ERROR_IRQ                       (1 << 13)
345 #define APBH_CTRL2_CH12_ERROR_IRQ                       (1 << 12)
346 #define APBH_CTRL2_CH11_ERROR_IRQ                       (1 << 11)
347 #define APBH_CTRL2_CH10_ERROR_IRQ                       (1 << 10)
348 #define APBH_CTRL2_CH9_ERROR_IRQ                        (1 << 9)
349 #define APBH_CTRL2_CH8_ERROR_IRQ                        (1 << 8)
350 #define APBH_CTRL2_CH7_ERROR_IRQ                        (1 << 7)
351 #define APBH_CTRL2_CH6_ERROR_IRQ                        (1 << 6)
352 #define APBH_CTRL2_CH5_ERROR_IRQ                        (1 << 5)
353 #define APBH_CTRL2_CH4_ERROR_IRQ                        (1 << 4)
354 #define APBH_CTRL2_CH3_ERROR_IRQ                        (1 << 3)
355 #define APBH_CTRL2_CH2_ERROR_IRQ                        (1 << 2)
356 #define APBH_CTRL2_CH1_ERROR_IRQ                        (1 << 1)
357 #define APBH_CTRL2_CH0_ERROR_IRQ                        (1 << 0)
358
359 #if defined(CONFIG_MX28)
360 #define APBH_CHANNEL_CTRL_RESET_CHANNEL_MASK            (0xffff << 16)
361 #define APBH_CHANNEL_CTRL_RESET_CHANNEL_OFFSET          16
362 #define APBH_CHANNEL_CTRL_RESET_CHANNEL_SSP0            (0x0001 << 16)
363 #define APBH_CHANNEL_CTRL_RESET_CHANNEL_SSP1            (0x0002 << 16)
364 #define APBH_CHANNEL_CTRL_RESET_CHANNEL_SSP2            (0x0004 << 16)
365 #define APBH_CHANNEL_CTRL_RESET_CHANNEL_SSP3            (0x0008 << 16)
366 #define APBH_CHANNEL_CTRL_RESET_CHANNEL_NAND0           (0x0010 << 16)
367 #define APBH_CHANNEL_CTRL_RESET_CHANNEL_NAND1           (0x0020 << 16)
368 #define APBH_CHANNEL_CTRL_RESET_CHANNEL_NAND2           (0x0040 << 16)
369 #define APBH_CHANNEL_CTRL_RESET_CHANNEL_NAND3           (0x0080 << 16)
370 #define APBH_CHANNEL_CTRL_RESET_CHANNEL_NAND4           (0x0100 << 16)
371 #define APBH_CHANNEL_CTRL_RESET_CHANNEL_NAND5           (0x0200 << 16)
372 #define APBH_CHANNEL_CTRL_RESET_CHANNEL_NAND6           (0x0400 << 16)
373 #define APBH_CHANNEL_CTRL_RESET_CHANNEL_NAND7           (0x0800 << 16)
374 #define APBH_CHANNEL_CTRL_RESET_CHANNEL_HSADC           (0x1000 << 16)
375 #define APBH_CHANNEL_CTRL_RESET_CHANNEL_LCDIF           (0x2000 << 16)
376 #define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_MASK           0xffff
377 #define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_OFFSET         0
378 #define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_SSP0           0x0001
379 #define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_SSP1           0x0002
380 #define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_SSP2           0x0004
381 #define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_SSP3           0x0008
382 #define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_NAND0          0x0010
383 #define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_NAND1          0x0020
384 #define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_NAND2          0x0040
385 #define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_NAND3          0x0080
386 #define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_NAND4          0x0100
387 #define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_NAND5          0x0200
388 #define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_NAND6          0x0400
389 #define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_NAND7          0x0800
390 #define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_HSADC          0x1000
391 #define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_LCDIF          0x2000
392 #endif
393
394 #if (defined(CONFIG_MX6) || defined(CONFIG_MX7))
395 #define APBH_CHANNEL_CTRL_RESET_CHANNEL_OFFSET          16
396 #endif
397
398 #if defined(CONFIG_MX23)
399 #define APBH_DEVSEL_CH7_MASK                            (0xf << 28)
400 #define APBH_DEVSEL_CH7_OFFSET                          28
401 #define APBH_DEVSEL_CH6_MASK                            (0xf << 24)
402 #define APBH_DEVSEL_CH6_OFFSET                          24
403 #define APBH_DEVSEL_CH5_MASK                            (0xf << 20)
404 #define APBH_DEVSEL_CH5_OFFSET                          20
405 #define APBH_DEVSEL_CH4_MASK                            (0xf << 16)
406 #define APBH_DEVSEL_CH4_OFFSET                          16
407 #define APBH_DEVSEL_CH3_MASK                            (0xf << 12)
408 #define APBH_DEVSEL_CH3_OFFSET                          12
409 #define APBH_DEVSEL_CH2_MASK                            (0xf << 8)
410 #define APBH_DEVSEL_CH2_OFFSET                          8
411 #define APBH_DEVSEL_CH1_MASK                            (0xf << 4)
412 #define APBH_DEVSEL_CH1_OFFSET                          4
413 #define APBH_DEVSEL_CH0_MASK                            (0xf << 0)
414 #define APBH_DEVSEL_CH0_OFFSET                          0
415 #elif defined(CONFIG_MX28)
416 #define APBH_DEVSEL_CH15_MASK                           (0x3 << 30)
417 #define APBH_DEVSEL_CH15_OFFSET                         30
418 #define APBH_DEVSEL_CH14_MASK                           (0x3 << 28)
419 #define APBH_DEVSEL_CH14_OFFSET                         28
420 #define APBH_DEVSEL_CH13_MASK                           (0x3 << 26)
421 #define APBH_DEVSEL_CH13_OFFSET                         26
422 #define APBH_DEVSEL_CH12_MASK                           (0x3 << 24)
423 #define APBH_DEVSEL_CH12_OFFSET                         24
424 #define APBH_DEVSEL_CH11_MASK                           (0x3 << 22)
425 #define APBH_DEVSEL_CH11_OFFSET                         22
426 #define APBH_DEVSEL_CH10_MASK                           (0x3 << 20)
427 #define APBH_DEVSEL_CH10_OFFSET                         20
428 #define APBH_DEVSEL_CH9_MASK                            (0x3 << 18)
429 #define APBH_DEVSEL_CH9_OFFSET                          18
430 #define APBH_DEVSEL_CH8_MASK                            (0x3 << 16)
431 #define APBH_DEVSEL_CH8_OFFSET                          16
432 #define APBH_DEVSEL_CH7_MASK                            (0x3 << 14)
433 #define APBH_DEVSEL_CH7_OFFSET                          14
434 #define APBH_DEVSEL_CH6_MASK                            (0x3 << 12)
435 #define APBH_DEVSEL_CH6_OFFSET                          12
436 #define APBH_DEVSEL_CH5_MASK                            (0x3 << 10)
437 #define APBH_DEVSEL_CH5_OFFSET                          10
438 #define APBH_DEVSEL_CH4_MASK                            (0x3 << 8)
439 #define APBH_DEVSEL_CH4_OFFSET                          8
440 #define APBH_DEVSEL_CH3_MASK                            (0x3 << 6)
441 #define APBH_DEVSEL_CH3_OFFSET                          6
442 #define APBH_DEVSEL_CH2_MASK                            (0x3 << 4)
443 #define APBH_DEVSEL_CH2_OFFSET                          4
444 #define APBH_DEVSEL_CH1_MASK                            (0x3 << 2)
445 #define APBH_DEVSEL_CH1_OFFSET                          2
446 #define APBH_DEVSEL_CH0_MASK                            (0x3 << 0)
447 #define APBH_DEVSEL_CH0_OFFSET                          0
448 #endif
449
450 #if defined(CONFIG_MX28)
451 #define APBH_DMA_BURST_SIZE_CH15_MASK                   (0x3 << 30)
452 #define APBH_DMA_BURST_SIZE_CH15_OFFSET                 30
453 #define APBH_DMA_BURST_SIZE_CH14_MASK                   (0x3 << 28)
454 #define APBH_DMA_BURST_SIZE_CH14_OFFSET                 28
455 #define APBH_DMA_BURST_SIZE_CH13_MASK                   (0x3 << 26)
456 #define APBH_DMA_BURST_SIZE_CH13_OFFSET                 26
457 #define APBH_DMA_BURST_SIZE_CH12_MASK                   (0x3 << 24)
458 #define APBH_DMA_BURST_SIZE_CH12_OFFSET                 24
459 #define APBH_DMA_BURST_SIZE_CH11_MASK                   (0x3 << 22)
460 #define APBH_DMA_BURST_SIZE_CH11_OFFSET                 22
461 #define APBH_DMA_BURST_SIZE_CH10_MASK                   (0x3 << 20)
462 #define APBH_DMA_BURST_SIZE_CH10_OFFSET                 20
463 #define APBH_DMA_BURST_SIZE_CH9_MASK                    (0x3 << 18)
464 #define APBH_DMA_BURST_SIZE_CH9_OFFSET                  18
465 #define APBH_DMA_BURST_SIZE_CH8_MASK                    (0x3 << 16)
466 #define APBH_DMA_BURST_SIZE_CH8_OFFSET                  16
467 #define APBH_DMA_BURST_SIZE_CH8_BURST0                  (0x0 << 16)
468 #define APBH_DMA_BURST_SIZE_CH8_BURST4                  (0x1 << 16)
469 #define APBH_DMA_BURST_SIZE_CH8_BURST8                  (0x2 << 16)
470 #define APBH_DMA_BURST_SIZE_CH7_MASK                    (0x3 << 14)
471 #define APBH_DMA_BURST_SIZE_CH7_OFFSET                  14
472 #define APBH_DMA_BURST_SIZE_CH6_MASK                    (0x3 << 12)
473 #define APBH_DMA_BURST_SIZE_CH6_OFFSET                  12
474 #define APBH_DMA_BURST_SIZE_CH5_MASK                    (0x3 << 10)
475 #define APBH_DMA_BURST_SIZE_CH5_OFFSET                  10
476 #define APBH_DMA_BURST_SIZE_CH4_MASK                    (0x3 << 8)
477 #define APBH_DMA_BURST_SIZE_CH4_OFFSET                  8
478 #define APBH_DMA_BURST_SIZE_CH3_MASK                    (0x3 << 6)
479 #define APBH_DMA_BURST_SIZE_CH3_OFFSET                  6
480 #define APBH_DMA_BURST_SIZE_CH3_BURST0                  (0x0 << 6)
481 #define APBH_DMA_BURST_SIZE_CH3_BURST4                  (0x1 << 6)
482 #define APBH_DMA_BURST_SIZE_CH3_BURST8                  (0x2 << 6)
483
484 #define APBH_DMA_BURST_SIZE_CH2_MASK                    (0x3 << 4)
485 #define APBH_DMA_BURST_SIZE_CH2_OFFSET                  4
486 #define APBH_DMA_BURST_SIZE_CH2_BURST0                  (0x0 << 4)
487 #define APBH_DMA_BURST_SIZE_CH2_BURST4                  (0x1 << 4)
488 #define APBH_DMA_BURST_SIZE_CH2_BURST8                  (0x2 << 4)
489 #define APBH_DMA_BURST_SIZE_CH1_MASK                    (0x3 << 2)
490 #define APBH_DMA_BURST_SIZE_CH1_OFFSET                  2
491 #define APBH_DMA_BURST_SIZE_CH1_BURST0                  (0x0 << 2)
492 #define APBH_DMA_BURST_SIZE_CH1_BURST4                  (0x1 << 2)
493 #define APBH_DMA_BURST_SIZE_CH1_BURST8                  (0x2 << 2)
494
495 #define APBH_DMA_BURST_SIZE_CH0_MASK                    0x3
496 #define APBH_DMA_BURST_SIZE_CH0_OFFSET                  0
497 #define APBH_DMA_BURST_SIZE_CH0_BURST0                  0x0
498 #define APBH_DMA_BURST_SIZE_CH0_BURST4                  0x1
499 #define APBH_DMA_BURST_SIZE_CH0_BURST8                  0x2
500
501 #define APBH_DEBUG_GPMI_ONE_FIFO                        (1 << 0)
502 #endif
503
504 #define APBH_CHn_CURCMDAR_CMD_ADDR_MASK                 0xffffffff
505 #define APBH_CHn_CURCMDAR_CMD_ADDR_OFFSET               0
506
507 #define APBH_CHn_NXTCMDAR_CMD_ADDR_MASK                 0xffffffff
508 #define APBH_CHn_NXTCMDAR_CMD_ADDR_OFFSET               0
509
510 #define APBH_CHn_CMD_XFER_COUNT_MASK                    (0xffff << 16)
511 #define APBH_CHn_CMD_XFER_COUNT_OFFSET                  16
512 #define APBH_CHn_CMD_CMDWORDS_MASK                      (0xf << 12)
513 #define APBH_CHn_CMD_CMDWORDS_OFFSET                    12
514 #define APBH_CHn_CMD_HALTONTERMINATE                    (1 << 8)
515 #define APBH_CHn_CMD_WAIT4ENDCMD                        (1 << 7)
516 #define APBH_CHn_CMD_SEMAPHORE                          (1 << 6)
517 #define APBH_CHn_CMD_NANDWAIT4READY                     (1 << 5)
518 #define APBH_CHn_CMD_NANDLOCK                           (1 << 4)
519 #define APBH_CHn_CMD_IRQONCMPLT                         (1 << 3)
520 #define APBH_CHn_CMD_CHAIN                              (1 << 2)
521 #define APBH_CHn_CMD_COMMAND_MASK                       0x3
522 #define APBH_CHn_CMD_COMMAND_OFFSET                     0
523 #define APBH_CHn_CMD_COMMAND_NO_DMA_XFER                0x0
524 #define APBH_CHn_CMD_COMMAND_DMA_WRITE                  0x1
525 #define APBH_CHn_CMD_COMMAND_DMA_READ                   0x2
526 #define APBH_CHn_CMD_COMMAND_DMA_SENSE                  0x3
527
528 #define APBH_CHn_BAR_ADDRESS_MASK                       0xffffffff
529 #define APBH_CHn_BAR_ADDRESS_OFFSET                     0
530
531 #define APBH_CHn_SEMA_RSVD2_MASK                        (0xff << 24)
532 #define APBH_CHn_SEMA_RSVD2_OFFSET                      24
533 #define APBH_CHn_SEMA_PHORE_MASK                        (0xff << 16)
534 #define APBH_CHn_SEMA_PHORE_OFFSET                      16
535 #define APBH_CHn_SEMA_RSVD1_MASK                        (0xff << 8)
536 #define APBH_CHn_SEMA_RSVD1_OFFSET                      8
537 #define APBH_CHn_SEMA_INCREMENT_SEMA_MASK               (0xff << 0)
538 #define APBH_CHn_SEMA_INCREMENT_SEMA_OFFSET             0
539
540 #define APBH_CHn_DEBUG1_REQ                             (1 << 31)
541 #define APBH_CHn_DEBUG1_BURST                           (1 << 30)
542 #define APBH_CHn_DEBUG1_KICK                            (1 << 29)
543 #define APBH_CHn_DEBUG1_END                             (1 << 28)
544 #define APBH_CHn_DEBUG1_SENSE                           (1 << 27)
545 #define APBH_CHn_DEBUG1_READY                           (1 << 26)
546 #define APBH_CHn_DEBUG1_LOCK                            (1 << 25)
547 #define APBH_CHn_DEBUG1_NEXTCMDADDRVALID                (1 << 24)
548 #define APBH_CHn_DEBUG1_RD_FIFO_EMPTY                   (1 << 23)
549 #define APBH_CHn_DEBUG1_RD_FIFO_FULL                    (1 << 22)
550 #define APBH_CHn_DEBUG1_WR_FIFO_EMPTY                   (1 << 21)
551 #define APBH_CHn_DEBUG1_WR_FIFO_FULL                    (1 << 20)
552 #define APBH_CHn_DEBUG1_RSVD1_MASK                      (0x7fff << 5)
553 #define APBH_CHn_DEBUG1_RSVD1_OFFSET                    5
554 #define APBH_CHn_DEBUG1_STATEMACHINE_MASK               0x1f
555 #define APBH_CHn_DEBUG1_STATEMACHINE_OFFSET             0
556 #define APBH_CHn_DEBUG1_STATEMACHINE_IDLE               0x00
557 #define APBH_CHn_DEBUG1_STATEMACHINE_REQ_CMD1           0x01
558 #define APBH_CHn_DEBUG1_STATEMACHINE_REQ_CMD3           0x02
559 #define APBH_CHn_DEBUG1_STATEMACHINE_REQ_CMD2           0x03
560 #define APBH_CHn_DEBUG1_STATEMACHINE_XFER_DECODE        0x04
561 #define APBH_CHn_DEBUG1_STATEMACHINE_REQ_WAIT           0x05
562 #define APBH_CHn_DEBUG1_STATEMACHINE_REQ_CMD4           0x06
563 #define APBH_CHn_DEBUG1_STATEMACHINE_PIO_REQ            0x07
564 #define APBH_CHn_DEBUG1_STATEMACHINE_READ_FLUSH         0x08
565 #define APBH_CHn_DEBUG1_STATEMACHINE_READ_WAIT          0x09
566 #define APBH_CHn_DEBUG1_STATEMACHINE_WRITE              0x0c
567 #define APBH_CHn_DEBUG1_STATEMACHINE_READ_REQ           0x0d
568 #define APBH_CHn_DEBUG1_STATEMACHINE_CHECK_CHAIN        0x0e
569 #define APBH_CHn_DEBUG1_STATEMACHINE_XFER_COMPLETE      0x0f
570 #define APBH_CHn_DEBUG1_STATEMACHINE_TERMINATE          0x14
571 #define APBH_CHn_DEBUG1_STATEMACHINE_WAIT_END           0x15
572 #define APBH_CHn_DEBUG1_STATEMACHINE_WRITE_WAIT         0x1c
573 #define APBH_CHn_DEBUG1_STATEMACHINE_HALT_AFTER_TERM    0x1d
574 #define APBH_CHn_DEBUG1_STATEMACHINE_CHECK_WAIT         0x1e
575 #define APBH_CHn_DEBUG1_STATEMACHINE_WAIT_READY         0x1f
576
577 #define APBH_CHn_DEBUG2_APB_BYTES_MASK                  (0xffff << 16)
578 #define APBH_CHn_DEBUG2_APB_BYTES_OFFSET                16
579 #define APBH_CHn_DEBUG2_AHB_BYTES_MASK                  0xffff
580 #define APBH_CHn_DEBUG2_AHB_BYTES_OFFSET                0
581
582 #define APBH_VERSION_MAJOR_MASK                         (0xff << 24)
583 #define APBH_VERSION_MAJOR_OFFSET                       24
584 #define APBH_VERSION_MINOR_MASK                         (0xff << 16)
585 #define APBH_VERSION_MINOR_OFFSET                       16
586 #define APBH_VERSION_STEP_MASK                          0xffff
587 #define APBH_VERSION_STEP_OFFSET                        0
588
589 #endif  /* __REGS_APBH_H__ */