1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright (C) 2016 Freescale Semiconductor, Inc.
10 * rdc_peri_cfg_t and rdc_ma_cft_t use the same layout.
12 * [ 23 22 | 21 20 | 19 18 | 17 16 ] | [ 15 - 8 ] | [ 7 - 0 ]
13 * d3 d2 d1 d0 | master id | peri id
14 * d[x] means domain[x], x can be [3 - 0].
16 typedef u32 rdc_peri_cfg_t;
17 typedef u32 rdc_ma_cfg_t;
19 #define RDC_PERI_SHIFT 0
20 #define RDC_PERI_MASK 0xFF
22 #define RDC_DOMAIN_SHIFT_BASE 16
23 #define RDC_DOMAIN_MASK 0xFF0000
24 #define RDC_DOMAIN_SHIFT(x) (RDC_DOMAIN_SHIFT_BASE + ((x << 1)))
25 #define RDC_DOMAIN(x) ((rdc_peri_cfg_t)(0x3 << RDC_DOMAIN_SHIFT(x)))
27 #define RDC_MASTER_SHIFT 8
28 #define RDC_MASTER_MASK 0xFF00
29 #define RDC_MASTER_CFG(master_id, domain_id) (rdc_ma_cfg_t)((master_id << 8) | \
30 (domain_id << RDC_DOMAIN_SHIFT_BASE))
32 /* The Following macro definitions are common to i.MX6SX and i.MX7D */
33 #define SEMA_GATES_NUM 64
35 #define RDC_MDA_DID_SHIFT 0
36 #define RDC_MDA_DID_MASK (0x3 << RDC_MDA_DID_SHIFT)
37 #define RDC_MDA_LCK_SHIFT 31
38 #define RDC_MDA_LCK_MASK (0x1 << RDC_MDA_LCK_SHIFT)
40 #define RDC_PDAP_DW_SHIFT(domain) ((domain) << 1)
41 #define RDC_PDAP_DR_SHIFT(domain) (1 + RDC_PDAP_DW_SHIFT(domain))
42 #define RDC_PDAP_DW_MASK(domain) (1 << RDC_PDAP_DW_SHIFT(domain))
43 #define RDC_PDAP_DR_MASK(domain) (1 << RDC_PDAP_DR_SHIFT(domain))
44 #define RDC_PDAP_DRW_MASK(domain) (RDC_PDAP_DW_MASK(domain) | \
45 RDC_PDAP_DR_MASK(domain))
47 #define RDC_PDAP_SREQ_SHIFT 30
48 #define RDC_PDAP_SREQ_MASK (0x1 << RDC_PDAP_SREQ_SHIFT)
49 #define RDC_PDAP_LCK_SHIFT 31
50 #define RDC_PDAP_LCK_MASK (0x1 << RDC_PDAP_LCK_SHIFT)
52 #define RDC_MRSA_SADR_SHIFT 7
53 #define RDC_MRSA_SADR_MASK (0x1ffffff << RDC_MRSA_SADR_SHIFT)
55 #define RDC_MREA_EADR_SHIFT 7
56 #define RDC_MREA_EADR_MASK (0x1ffffff << RDC_MREA_EADR_SHIFT)
58 #define RDC_MRC_DW_SHIFT(domain) (domain)
59 #define RDC_MRC_DR_SHIFT(domain) (1 + RDC_MRC_DW_SHIFT(domain))
60 #define RDC_MRC_DW_MASK(domain) (1 << RDC_MRC_DW_SHIFT(domain))
61 #define RDC_MRC_DR_MASK(domain) (1 << RDC_MRC_DR_SHIFT(domain))
62 #define RDC_MRC_DRW_MASK(domain) (RDC_MRC_DW_MASK(domain) | \
63 RDC_MRC_DR_MASK(domain))
64 #define RDC_MRC_ENA_SHIFT 30
65 #define RDC_MRC_ENA_MASK (0x1 << RDC_MRC_ENA_SHIFT)
66 #define RDC_MRC_LCK_SHIFT 31
67 #define RDC_MRC_LCK_MASK (0x1 << RDC_MRC_LCK_SHIFT)
69 #define RDC_MRVS_VDID_SHIFT 0
70 #define RDC_MRVS_VDID_MASK (0x3 << RDC_MRVS_VDID_SHIFT)
71 #define RDC_MRVS_AD_SHIFT 4
72 #define RDC_MRVS_AD_MASK (0x1 << RDC_MRVS_AD_SHIFT)
73 #define RDC_MRVS_VADDR_SHIFT 5
74 #define RDC_MRVS_VADDR_MASK (0x7ffffff << RDC_MRVS_VADDR_SHIFT)
76 #define RDC_SEMA_GATE_GTFSM_SHIFT 0
77 #define RDC_SEMA_GATE_GTFSM_MASK (0xf << RDC_SEMA_GATE_GTFSM_SHIFT)
78 #define RDC_SEMA_GATE_LDOM_SHIFT 5
79 #define RDC_SEMA_GATE_LDOM_MASK (0x3 << RDC_SEMA_GATE_LDOM_SHIFT)
81 #define RDC_SEMA_RSTGT_RSTGDP_SHIFT 0
82 #define RDC_SEMA_RSTGT_RSTGDP_MASK (0xff << RDC_SEMA_RSTGT_RSTGDP_SHIFT)
83 #define RDC_SEMA_RSTGT_RSTGSM_SHIFT 2
84 #define RDC_SEMA_RSTGT_RSTGSM_MASK (0x3 << RDC_SEMA_RSTGT_RSTGSM_SHIFT)
85 #define RDC_SEMA_RSTGT_RSTGMS_SHIFT 4
86 #define RDC_SEMA_RSTGT_RSTGMS_MASK (0xf << RDC_SEMA_RSTGT_RSTGMS_SHIFT)
87 #define RDC_SEMA_RSTGT_RSTGTN_SHIFT 8
88 #define RDC_SEMA_RSTGT_RSTGTN_MASK (0xff << RDC_SEMA_RSTGT_RSTGTN_SHIFT)
90 int imx_rdc_check_permission(int per_id, int dom_id);
91 int imx_rdc_sema_lock(int per_id);
92 int imx_rdc_sema_unlock(int per_id);
93 int imx_rdc_setup_peri(rdc_peri_cfg_t p);
94 int imx_rdc_setup_peripherals(rdc_peri_cfg_t const *peripherals_list,
96 int imx_rdc_setup_ma(rdc_ma_cfg_t p);
97 int imx_rdc_setup_masters(rdc_ma_cfg_t const *masters_list, unsigned count);
99 #endif /* __RDC_SEMA_H__*/