1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Freescale i.MX28 APBH DMA
5 * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
6 * on behalf of DENX Software Engineering GmbH
8 * Based on code from LTIB:
9 * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved.
16 #include <asm/cache.h>
17 #include <linux/list.h>
18 #include <linux/compiler.h>
20 #define DMA_PIO_WORDS 15
21 #define MXS_DMA_ALIGNMENT ARCH_DMA_MINALIGN
26 #if defined(CONFIG_MX23)
28 MXS_DMA_CHANNEL_AHB_APBH_LCDIF = 0,
29 MXS_DMA_CHANNEL_AHB_APBH_SSP0,
30 MXS_DMA_CHANNEL_AHB_APBH_SSP1,
31 MXS_DMA_CHANNEL_AHB_APBH_RESERVED0,
32 MXS_DMA_CHANNEL_AHB_APBH_GPMI0,
33 MXS_DMA_CHANNEL_AHB_APBH_GPMI1,
34 MXS_DMA_CHANNEL_AHB_APBH_GPMI2,
35 MXS_DMA_CHANNEL_AHB_APBH_GPMI3,
38 #elif defined(CONFIG_MX28)
40 MXS_DMA_CHANNEL_AHB_APBH_SSP0 = 0,
41 MXS_DMA_CHANNEL_AHB_APBH_SSP1,
42 MXS_DMA_CHANNEL_AHB_APBH_SSP2,
43 MXS_DMA_CHANNEL_AHB_APBH_SSP3,
44 MXS_DMA_CHANNEL_AHB_APBH_GPMI0,
45 MXS_DMA_CHANNEL_AHB_APBH_GPMI1,
46 MXS_DMA_CHANNEL_AHB_APBH_GPMI2,
47 MXS_DMA_CHANNEL_AHB_APBH_GPMI3,
48 MXS_DMA_CHANNEL_AHB_APBH_GPMI4,
49 MXS_DMA_CHANNEL_AHB_APBH_GPMI5,
50 MXS_DMA_CHANNEL_AHB_APBH_GPMI6,
51 MXS_DMA_CHANNEL_AHB_APBH_GPMI7,
52 MXS_DMA_CHANNEL_AHB_APBH_HSADC,
53 MXS_DMA_CHANNEL_AHB_APBH_LCDIF,
54 MXS_DMA_CHANNEL_AHB_APBH_RESERVED0,
55 MXS_DMA_CHANNEL_AHB_APBH_RESERVED1,
60 MXS_DMA_CHANNEL_AHB_APBH_GPMI0 = 0,
61 MXS_DMA_CHANNEL_AHB_APBH_GPMI1,
62 MXS_DMA_CHANNEL_AHB_APBH_GPMI2,
63 MXS_DMA_CHANNEL_AHB_APBH_GPMI3,
64 MXS_DMA_CHANNEL_AHB_APBH_GPMI4,
65 MXS_DMA_CHANNEL_AHB_APBH_GPMI5,
66 MXS_DMA_CHANNEL_AHB_APBH_GPMI6,
67 MXS_DMA_CHANNEL_AHB_APBH_GPMI7,
73 * MXS DMA hardware command.
75 * This structure describes the in-memory layout of an entire DMA command,
76 * including space for the maximum number of PIO accesses. See the appropriate
77 * reference manual for a detailed description of what these fields mean to the
80 #define MXS_DMA_DESC_COMMAND_MASK 0x3
81 #define MXS_DMA_DESC_COMMAND_OFFSET 0
82 #define MXS_DMA_DESC_COMMAND_NO_DMAXFER 0x0
83 #define MXS_DMA_DESC_COMMAND_DMA_WRITE 0x1
84 #define MXS_DMA_DESC_COMMAND_DMA_READ 0x2
85 #define MXS_DMA_DESC_COMMAND_DMA_SENSE 0x3
86 #define MXS_DMA_DESC_CHAIN (1 << 2)
87 #define MXS_DMA_DESC_IRQ (1 << 3)
88 #define MXS_DMA_DESC_NAND_LOCK (1 << 4)
89 #define MXS_DMA_DESC_NAND_WAIT_4_READY (1 << 5)
90 #define MXS_DMA_DESC_DEC_SEM (1 << 6)
91 #define MXS_DMA_DESC_WAIT4END (1 << 7)
92 #define MXS_DMA_DESC_HALT_ON_TERMINATE (1 << 8)
93 #define MXS_DMA_DESC_TERMINATE_FLUSH (1 << 9)
94 #define MXS_DMA_DESC_PIO_WORDS_MASK (0xf << 12)
95 #define MXS_DMA_DESC_PIO_WORDS_OFFSET 12
96 #define MXS_DMA_DESC_BYTES_MASK (0xffff << 16)
97 #define MXS_DMA_DESC_BYTES_OFFSET 16
106 u32 pio_words[DMA_PIO_WORDS];
110 * MXS DMA command descriptor.
112 * This structure incorporates an MXS DMA hardware command structure, along
115 #define MXS_DMA_DESC_FIRST (1 << 0)
116 #define MXS_DMA_DESC_LAST (1 << 1)
117 #define MXS_DMA_DESC_READY (1 << 31)
119 struct mxs_dma_desc {
120 struct mxs_dma_cmd cmd;
124 struct list_head node;
125 } __aligned(MXS_DMA_ALIGNMENT);
130 * This structure represents a single DMA channel. The MXS platform code
131 * maintains an array of these structures to represent every DMA channel in the
132 * system (see mxs_dma_channels).
134 #define MXS_DMA_FLAGS_IDLE 0
135 #define MXS_DMA_FLAGS_BUSY (1 << 0)
136 #define MXS_DMA_FLAGS_FREE 0
137 #define MXS_DMA_FLAGS_ALLOCATED (1 << 16)
138 #define MXS_DMA_FLAGS_VALID (1 << 31)
140 struct mxs_dma_chan {
143 struct mxs_dma_device *dma;
145 unsigned int active_num;
146 unsigned int pending_num;
147 struct list_head active;
148 struct list_head done;
151 struct mxs_dma_desc *mxs_dma_desc_alloc(void);
152 void mxs_dma_desc_free(struct mxs_dma_desc *);
153 int mxs_dma_desc_append(int channel, struct mxs_dma_desc *pdesc);
155 int mxs_dma_go(int chan);
156 void mxs_dma_init(void);
157 int mxs_dma_init_channel(int chan);
158 int mxs_dma_release(int chan);
160 void mxs_dma_circ_start(int chan, struct mxs_dma_desc *pdesc);
162 #endif /* __DMA_H__ */