2 * Freescale i.MX28 APBH DMA
4 * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
5 * on behalf of DENX Software Engineering GmbH
7 * Based on code from LTIB:
8 * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved.
10 * SPDX-License-Identifier: GPL-2.0+
16 #include <linux/list.h>
17 #include <linux/compiler.h>
19 #define DMA_PIO_WORDS 15
20 #define MXS_DMA_ALIGNMENT ARCH_DMA_MINALIGN
25 #if defined(CONFIG_MX23)
27 MXS_DMA_CHANNEL_AHB_APBH_LCDIF = 0,
28 MXS_DMA_CHANNEL_AHB_APBH_SSP0,
29 MXS_DMA_CHANNEL_AHB_APBH_SSP1,
30 MXS_DMA_CHANNEL_AHB_APBH_RESERVED0,
31 MXS_DMA_CHANNEL_AHB_APBH_GPMI0,
32 MXS_DMA_CHANNEL_AHB_APBH_GPMI1,
33 MXS_DMA_CHANNEL_AHB_APBH_GPMI2,
34 MXS_DMA_CHANNEL_AHB_APBH_GPMI3,
37 #elif defined(CONFIG_MX28)
39 MXS_DMA_CHANNEL_AHB_APBH_SSP0 = 0,
40 MXS_DMA_CHANNEL_AHB_APBH_SSP1,
41 MXS_DMA_CHANNEL_AHB_APBH_SSP2,
42 MXS_DMA_CHANNEL_AHB_APBH_SSP3,
43 MXS_DMA_CHANNEL_AHB_APBH_GPMI0,
44 MXS_DMA_CHANNEL_AHB_APBH_GPMI1,
45 MXS_DMA_CHANNEL_AHB_APBH_GPMI2,
46 MXS_DMA_CHANNEL_AHB_APBH_GPMI3,
47 MXS_DMA_CHANNEL_AHB_APBH_GPMI4,
48 MXS_DMA_CHANNEL_AHB_APBH_GPMI5,
49 MXS_DMA_CHANNEL_AHB_APBH_GPMI6,
50 MXS_DMA_CHANNEL_AHB_APBH_GPMI7,
51 MXS_DMA_CHANNEL_AHB_APBH_HSADC,
52 MXS_DMA_CHANNEL_AHB_APBH_LCDIF,
53 MXS_DMA_CHANNEL_AHB_APBH_RESERVED0,
54 MXS_DMA_CHANNEL_AHB_APBH_RESERVED1,
57 #elif defined(CONFIG_MX6) || defined(CONFIG_MX7)
59 MXS_DMA_CHANNEL_AHB_APBH_GPMI0 = 0,
60 MXS_DMA_CHANNEL_AHB_APBH_GPMI1,
61 MXS_DMA_CHANNEL_AHB_APBH_GPMI2,
62 MXS_DMA_CHANNEL_AHB_APBH_GPMI3,
63 MXS_DMA_CHANNEL_AHB_APBH_GPMI4,
64 MXS_DMA_CHANNEL_AHB_APBH_GPMI5,
65 MXS_DMA_CHANNEL_AHB_APBH_GPMI6,
66 MXS_DMA_CHANNEL_AHB_APBH_GPMI7,
72 * MXS DMA hardware command.
74 * This structure describes the in-memory layout of an entire DMA command,
75 * including space for the maximum number of PIO accesses. See the appropriate
76 * reference manual for a detailed description of what these fields mean to the
79 #define MXS_DMA_DESC_COMMAND_MASK 0x3
80 #define MXS_DMA_DESC_COMMAND_OFFSET 0
81 #define MXS_DMA_DESC_COMMAND_NO_DMAXFER 0x0
82 #define MXS_DMA_DESC_COMMAND_DMA_WRITE 0x1
83 #define MXS_DMA_DESC_COMMAND_DMA_READ 0x2
84 #define MXS_DMA_DESC_COMMAND_DMA_SENSE 0x3
85 #define MXS_DMA_DESC_CHAIN (1 << 2)
86 #define MXS_DMA_DESC_IRQ (1 << 3)
87 #define MXS_DMA_DESC_NAND_LOCK (1 << 4)
88 #define MXS_DMA_DESC_NAND_WAIT_4_READY (1 << 5)
89 #define MXS_DMA_DESC_DEC_SEM (1 << 6)
90 #define MXS_DMA_DESC_WAIT4END (1 << 7)
91 #define MXS_DMA_DESC_HALT_ON_TERMINATE (1 << 8)
92 #define MXS_DMA_DESC_TERMINATE_FLUSH (1 << 9)
93 #define MXS_DMA_DESC_PIO_WORDS_MASK (0xf << 12)
94 #define MXS_DMA_DESC_PIO_WORDS_OFFSET 12
95 #define MXS_DMA_DESC_BYTES_MASK (0xffff << 16)
96 #define MXS_DMA_DESC_BYTES_OFFSET 16
103 unsigned long alternate;
105 unsigned long pio_words[DMA_PIO_WORDS];
109 * MXS DMA command descriptor.
111 * This structure incorporates an MXS DMA hardware command structure, along
114 #define MXS_DMA_DESC_FIRST (1 << 0)
115 #define MXS_DMA_DESC_LAST (1 << 1)
116 #define MXS_DMA_DESC_READY (1 << 31)
118 struct mxs_dma_desc {
119 struct mxs_dma_cmd cmd;
123 struct list_head node;
124 } __aligned(MXS_DMA_ALIGNMENT);
129 * This structure represents a single DMA channel. The MXS platform code
130 * maintains an array of these structures to represent every DMA channel in the
131 * system (see mxs_dma_channels).
133 #define MXS_DMA_FLAGS_IDLE 0
134 #define MXS_DMA_FLAGS_BUSY (1 << 0)
135 #define MXS_DMA_FLAGS_FREE 0
136 #define MXS_DMA_FLAGS_ALLOCATED (1 << 16)
137 #define MXS_DMA_FLAGS_VALID (1 << 31)
139 struct mxs_dma_chan {
142 struct mxs_dma_device *dma;
144 unsigned int active_num;
145 unsigned int pending_num;
146 struct list_head active;
147 struct list_head done;
150 struct mxs_dma_desc *mxs_dma_desc_alloc(void);
151 void mxs_dma_desc_free(struct mxs_dma_desc *);
152 int mxs_dma_desc_append(int channel, struct mxs_dma_desc *pdesc);
154 int mxs_dma_go(int chan);
155 void mxs_dma_init(void);
156 int mxs_dma_init_channel(int chan);
157 int mxs_dma_release(int chan);
159 void mxs_dma_circ_start(int chan, struct mxs_dma_desc *pdesc);
161 #endif /* __DMA_H__ */