2 * Based on Linux i.MX iomux-v3.h file:
3 * Copyright (C) 2009 by Jan Weitzel Phytec Messtechnik GmbH,
6 * Copyright (C) 2011 Freescale Semiconductor, Inc.
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * as published by the Free Software Foundation; either version 2
11 * of the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
23 #ifndef __MACH_IOMUX_V3_H__
24 #define __MACH_IOMUX_V3_H__
29 * build IOMUX_PAD structure
31 * This iomux scheme is based around pads, which are the physical balls
34 * - Each pad has a pad control register (IOMUXC_SW_PAD_CTRL_x) which controls
35 * things like driving strength and pullup/pulldown.
36 * - Each pad can have but not necessarily does have an output routing register
37 * (IOMUXC_SW_MUX_CTL_PAD_x).
38 * - Each pad can have but not necessarily does have an input routing register
39 * (IOMUXC_x_SELECT_INPUT)
41 * The three register sets do not have a fixed offset to each other,
42 * hence we order this table by pad control registers (which all pads
43 * have) and put the optional i/o routing registers into additional
46 * The naming convention for the pad modes is SOC_PAD_<padname>__<padmode>
47 * If <padname> or <padmode> refers to a GPIO, it is named GPIO_<unit>_<num>
49 * IOMUX/PAD Bit field definitions
51 * MUX_CTRL_OFS: 0..11 (12)
52 * PAD_CTRL_OFS: 12..23 (12)
53 * SEL_INPUT_OFS: 24..35 (12)
54 * MUX_MODE + SION: 36..40 (5)
55 * PAD_CTRL + NO_PAD_CTRL: 41..58 (18)
60 typedef u64 iomux_v3_cfg_t;
62 #define MUX_CTRL_OFS_SHIFT 0
63 #define MUX_CTRL_OFS_MASK ((iomux_v3_cfg_t)0xfff << MUX_CTRL_OFS_SHIFT)
64 #define MUX_PAD_CTRL_OFS_SHIFT 12
65 #define MUX_PAD_CTRL_OFS_MASK ((iomux_v3_cfg_t)0xfff << \
66 MUX_PAD_CTRL_OFS_SHIFT)
67 #define MUX_SEL_INPUT_OFS_SHIFT 24
68 #define MUX_SEL_INPUT_OFS_MASK ((iomux_v3_cfg_t)0xfff << \
69 MUX_SEL_INPUT_OFS_SHIFT)
71 #define MUX_MODE_SHIFT 36
72 #define MUX_MODE_MASK ((iomux_v3_cfg_t)0x1f << MUX_MODE_SHIFT)
73 #define MUX_PAD_CTRL_SHIFT 41
74 #define MUX_PAD_CTRL_MASK ((iomux_v3_cfg_t)0x3ffff << MUX_PAD_CTRL_SHIFT)
75 #define MUX_SEL_INPUT_SHIFT 59
76 #define MUX_SEL_INPUT_MASK ((iomux_v3_cfg_t)0xf << MUX_SEL_INPUT_SHIFT)
78 #define MUX_PAD_CTRL(x) ((iomux_v3_cfg_t)(x) << MUX_PAD_CTRL_SHIFT)
80 #define IOMUX_PAD(pad_ctrl_ofs, mux_ctrl_ofs, mux_mode, sel_input_ofs, \
81 sel_input, pad_ctrl) \
82 (((iomux_v3_cfg_t)(mux_ctrl_ofs) << MUX_CTRL_OFS_SHIFT) | \
83 ((iomux_v3_cfg_t)(mux_mode) << MUX_MODE_SHIFT) | \
84 ((iomux_v3_cfg_t)(pad_ctrl_ofs) << MUX_PAD_CTRL_OFS_SHIFT) | \
85 ((iomux_v3_cfg_t)(pad_ctrl) << MUX_PAD_CTRL_SHIFT) | \
86 ((iomux_v3_cfg_t)(sel_input_ofs) << MUX_SEL_INPUT_OFS_SHIFT)| \
87 ((iomux_v3_cfg_t)(sel_input) << MUX_SEL_INPUT_SHIFT))
93 #define NO_PAD_CTRL (1 << 17)
97 #define PAD_CTL_HYS (1 << 16)
99 #define PAD_CTL_PUS_100K_DOWN (0 << 14)
100 #define PAD_CTL_PUS_47K_UP (1 << 14)
101 #define PAD_CTL_PUS_100K_UP (2 << 14)
102 #define PAD_CTL_PUS_22K_UP (3 << 14)
103 #define PAD_CTL_PUE (1 << 13)
104 #define PAD_CTL_PKE (1 << 12)
106 #define PAD_CTL_ODE (1 << 11)
108 #define PAD_CTL_SPEED_LOW (1 << 6)
109 #define PAD_CTL_SPEED_MED (2 << 6)
110 #define PAD_CTL_SPEED_HIGH (3 << 6)
112 #define PAD_CTL_DSE_DISABLE (0 << 3)
113 #define PAD_CTL_DSE_240ohm (1 << 3)
114 #define PAD_CTL_DSE_120ohm (2 << 3)
115 #define PAD_CTL_DSE_80ohm (3 << 3)
116 #define PAD_CTL_DSE_60ohm (4 << 3)
117 #define PAD_CTL_DSE_48ohm (5 << 3)
118 #define PAD_CTL_DSE_40ohm (6 << 3)
119 #define PAD_CTL_DSE_34ohm (7 << 3)
123 #define PAD_CTL_DVS (1 << 13)
124 #define PAD_CTL_INPUT_DDR (1 << 9)
125 #define PAD_CTL_HYS (1 << 8)
127 #define PAD_CTL_PKE (1 << 7)
128 #define PAD_CTL_PUE (1 << 6 | PAD_CTL_PKE)
129 #define PAD_CTL_PUS_100K_DOWN (0 << 4 | PAD_CTL_PUE)
130 #define PAD_CTL_PUS_47K_UP (1 << 4 | PAD_CTL_PUE)
131 #define PAD_CTL_PUS_100K_UP (2 << 4 | PAD_CTL_PUE)
132 #define PAD_CTL_PUS_22K_UP (3 << 4 | PAD_CTL_PUE)
134 #define PAD_CTL_ODE (1 << 3)
136 #define PAD_CTL_DSE_LOW (0 << 1)
137 #define PAD_CTL_DSE_MED (1 << 1)
138 #define PAD_CTL_DSE_HIGH (2 << 1)
139 #define PAD_CTL_DSE_MAX (3 << 1)
143 #define PAD_CTL_SRE_SLOW (0 << 0)
144 #define PAD_CTL_SRE_FAST (1 << 0)
146 #define IOMUX_CONFIG_SION 0x10
148 #define GPIO_PIN_MASK 0x1f
149 #define GPIO_PORT_SHIFT 5
150 #define GPIO_PORT_MASK (0x7 << GPIO_PORT_SHIFT)
151 #define GPIO_PORTA (0 << GPIO_PORT_SHIFT)
152 #define GPIO_PORTB (1 << GPIO_PORT_SHIFT)
153 #define GPIO_PORTC (2 << GPIO_PORT_SHIFT)
154 #define GPIO_PORTD (3 << GPIO_PORT_SHIFT)
155 #define GPIO_PORTE (4 << GPIO_PORT_SHIFT)
156 #define GPIO_PORTF (5 << GPIO_PORT_SHIFT)
158 void imx_iomux_v3_setup_pad(iomux_v3_cfg_t pad);
159 void imx_iomux_v3_setup_multiple_pads(iomux_v3_cfg_t const *pad_list,
162 #endif /* __MACH_IOMUX_V3_H__*/