3 * David Feng <fenghua@phytium.com.cn>
5 * SPDX-License-Identifier: GPL-2.0+
8 #ifndef _ASM_ARMV8_MMU_H_
9 #define _ASM_ARMV8_MMU_H_
14 #define _AC(X, Y) (X##Y)
17 #define UL(x) _AC(x, UL)
19 /***************************************************************/
21 * The following definitions are related each other, shoud be
22 * calculated specifically.
25 #ifndef CONFIG_SYS_FULL_VA
26 #define VA_BITS (42) /* 42 bits virtual address */
28 #define VA_BITS CONFIG_SYS_VA_BITS
29 #define PTE_BLOCK_BITS CONFIG_SYS_PTL2_BITS
33 * block/section address mask and size definitions.
35 #ifndef CONFIG_SYS_FULL_VA
36 #define SECTION_SHIFT 29
37 #define SECTION_SIZE (UL(1) << SECTION_SHIFT)
38 #define SECTION_MASK (~(SECTION_SIZE-1))
40 /* PAGE_SHIFT determines the page size */
43 #define PAGE_SIZE (1 << PAGE_SHIFT)
44 #define PAGE_MASK (~(PAGE_SIZE-1))
48 /* PAGE_SHIFT determines the page size */
51 #define PAGE_SIZE (1 << PAGE_SHIFT)
52 #define PAGE_MASK (~(PAGE_SIZE-1))
56 /***************************************************************/
61 #define MT_DEVICE_NGNRNE 0
62 #define MT_DEVICE_NGNRE 1
63 #define MT_DEVICE_GRE 2
64 #define MT_NORMAL_NC 3
67 #define MEMORY_ATTRIBUTES ((0x00 << (MT_DEVICE_NGNRNE * 8)) | \
68 (0x04 << (MT_DEVICE_NGNRE * 8)) | \
69 (0x0c << (MT_DEVICE_GRE * 8)) | \
70 (0x44 << (MT_NORMAL_NC * 8)) | \
71 (UL(0xff) << (MT_NORMAL * 8)))
74 * Hardware page table definitions.
78 #ifdef CONFIG_SYS_FULL_VA
80 #define PTE_TYPE_MASK (3 << 0)
81 #define PTE_TYPE_FAULT (0 << 0)
82 #define PTE_TYPE_TABLE (3 << 0)
83 #define PTE_TYPE_BLOCK (1 << 0)
85 #define PTE_TABLE_PXN (1UL << 59)
86 #define PTE_TABLE_XN (1UL << 60)
87 #define PTE_TABLE_AP (1UL << 61)
88 #define PTE_TABLE_NS (1UL << 63)
93 #define PTE_BLOCK_MEMTYPE(x) ((x) << 2)
94 #define PTE_BLOCK_NON_SHARE (0 << 8)
95 #define PTE_BLOCK_OUTER_SHARE (2 << 8)
96 #define PTE_BLOCK_INNER_SHARE (3 << 8)
97 #define PTE_BLOCK_AF (1 << 10)
98 #define PTE_BLOCK_NG (1 << 11)
99 #define PTE_BLOCK_PXN (UL(1) << 53)
100 #define PTE_BLOCK_UXN (UL(1) << 54)
104 * Level 2 descriptor (PMD).
106 #define PMD_TYPE_MASK (3 << 0)
107 #define PMD_TYPE_FAULT (0 << 0)
108 #define PMD_TYPE_TABLE (3 << 0)
109 #define PMD_TYPE_SECT (1 << 0)
114 #define PMD_SECT_NS (1 << 5)
115 #define PMD_SECT_NON_SHARE (0 << 8)
116 #define PMD_SECT_OUTER_SHARE (2 << 8)
117 #define PMD_SECT_INNER_SHARE (3 << 8)
118 #define PMD_SECT_AF (1 << 10)
119 #define PMD_SECT_NG (1 << 11)
120 #define PMD_SECT_PXN (UL(1) << 53)
121 #define PMD_SECT_UXN (UL(1) << 54)
128 #define PMD_ATTRINDX(t) ((t) << 2)
129 #define PMD_ATTRINDX_MASK (7 << 2)
134 #define TCR_T0SZ(x) ((64 - (x)) << 0)
135 #define TCR_IRGN_NC (0 << 8)
136 #define TCR_IRGN_WBWA (1 << 8)
137 #define TCR_IRGN_WT (2 << 8)
138 #define TCR_IRGN_WBNWA (3 << 8)
139 #define TCR_IRGN_MASK (3 << 8)
140 #define TCR_ORGN_NC (0 << 10)
141 #define TCR_ORGN_WBWA (1 << 10)
142 #define TCR_ORGN_WT (2 << 10)
143 #define TCR_ORGN_WBNWA (3 << 10)
144 #define TCR_ORGN_MASK (3 << 10)
145 #define TCR_SHARED_NON (0 << 12)
146 #define TCR_SHARED_OUTER (2 << 12)
147 #define TCR_SHARED_INNER (3 << 12)
148 #define TCR_TG0_4K (0 << 14)
149 #define TCR_TG0_64K (1 << 14)
150 #define TCR_TG0_16K (2 << 14)
151 #define TCR_EPD1_DISABLE (1 << 23)
153 #ifndef CONFIG_SYS_FULL_VA
154 #define TCR_EL1_IPS_BITS (UL(3) << 32) /* 42 bits physical address */
155 #define TCR_EL2_IPS_BITS (3 << 16) /* 42 bits physical address */
156 #define TCR_EL3_IPS_BITS (3 << 16) /* 42 bits physical address */
158 /* PTWs cacheable, inner/outer WBWA and inner shareable */
159 #define TCR_FLAGS (TCR_TG0_64K | \
166 #define TCR_EL1_RSVD (1 << 31)
167 #define TCR_EL2_RSVD (1 << 31 | 1 << 23)
168 #define TCR_EL3_RSVD (1 << 31 | 1 << 23)
171 #ifndef CONFIG_SYS_FULL_VA
173 void set_pgtable_section(u64 *page_table, u64 index,
174 u64 section, u64 memory_type,
176 void set_pgtable_table(u64 *page_table, u64 index,
180 static inline void set_ttbr_tcr_mair(int el, u64 table, u64 tcr, u64 attr)
182 asm volatile("dsb sy");
184 asm volatile("msr ttbr0_el1, %0" : : "r" (table) : "memory");
185 asm volatile("msr tcr_el1, %0" : : "r" (tcr) : "memory");
186 asm volatile("msr mair_el1, %0" : : "r" (attr) : "memory");
187 } else if (el == 2) {
188 asm volatile("msr ttbr0_el2, %0" : : "r" (table) : "memory");
189 asm volatile("msr tcr_el2, %0" : : "r" (tcr) : "memory");
190 asm volatile("msr mair_el2, %0" : : "r" (attr) : "memory");
191 } else if (el == 3) {
192 asm volatile("msr ttbr0_el3, %0" : : "r" (table) : "memory");
193 asm volatile("msr tcr_el3, %0" : : "r" (tcr) : "memory");
194 asm volatile("msr mair_el3, %0" : : "r" (attr) : "memory");
207 extern struct mm_region *mem_map;
210 #endif /* _ASM_ARMV8_MMU_H_ */