arch/arm/include/asm/armv7m.h

   1 /*
   2  * (C) Copyright 2010,2011
   3  * Vladimir Khusainov, Emcraft Systems, vlad@emcraft.com
   4  *
   5  * (C) Copyright 2015
   6  * Kamil Lulko, <kamil.lulko@gmail.com>
   7  *
   8  * SPDX-License-Identifier:     GPL-2.0+
   9  */
  10
  11 #ifndef ARMV7M_H
  12 #define ARMV7M_H
  13
  14 #if defined(__ASSEMBLY__)
  15 .syntax unified
  16 .thumb
  17 #endif
  18
  19 #define V7M_SCB_BASE            0xE000ED00
  20 #define V7M_MPU_BASE            0xE000ED90
  21
  22 #define V7M_SCB_VTOR            0x08
  23
  24 #if !defined(__ASSEMBLY__)
  25 struct v7m_scb {
  26         uint32_t cpuid;         /* CPUID Base Register */
  27         uint32_t icsr;          /* Interrupt Control and State Register */
  28         uint32_t vtor;          /* Vector Table Offset Register */
  29         uint32_t aircr;         /* App Interrupt and Reset Control Register */
  30 };
  31 #define V7M_SCB                         ((struct v7m_scb *)V7M_SCB_BASE)
  32
  33 #define V7M_AIRCR_VECTKEY               0x5fa
  34 #define V7M_AIRCR_VECTKEY_SHIFT         16
  35 #define V7M_AIRCR_ENDIAN                (1 << 15)
  36 #define V7M_AIRCR_PRIGROUP_SHIFT        8
  37 #define V7M_AIRCR_PRIGROUP_MSK          (0x7 << V7M_AIRCR_PRIGROUP_SHIFT)
  38 #define V7M_AIRCR_SYSRESET              (1 << 2)
  39
  40 #define V7M_ICSR_VECTACT_MSK            0xFF
  41
  42 struct v7m_mpu {
  43         uint32_t type;          /* Type Register */
  44         uint32_t ctrl;          /* Control Register */
  45         uint32_t rnr;           /* Region Number Register */
  46         uint32_t rbar;          /* Region Base Address Register */
  47         uint32_t rasr;          /* Region Attribute and Size Register */
  48 };
  49 #define V7M_MPU                         ((struct v7m_mpu *)V7M_MPU_BASE)
  50
  51 #define V7M_MPU_CTRL_ENABLE             (1 << 0)
  52 #define V7M_MPU_CTRL_HFNMIENA           (1 << 1)
  53
  54 #define V7M_MPU_CTRL_ENABLE             (1 << 0)
  55 #define V7M_MPU_CTRL_DISABLE            (0 << 0)
  56 #define V7M_MPU_CTRL_HFNMIENA           (1 << 1)
  57
  58 #define V7M_MPU_RASR_EN                 (1 << 0)
  59 #define V7M_MPU_RASR_SIZE_BITS          1
  60 #define V7M_MPU_RASR_SIZE_4GB           (31 << V7M_MPU_RASR_SIZE_BITS)
  61 #define V7M_MPU_RASR_SIZE_8MB           (24 << V7M_MPU_RASR_SIZE_BITS)
  62 #define V7M_MPU_RASR_TEX_SHIFT  19
  63 #define V7M_MPU_RASR_S_SHIFT            18
  64 #define V7M_MPU_RASR_C_SHIFT            17
  65 #define V7M_MPU_RASR_B_SHIFT            16
  66 #define V7M_MPU_RASR_AP_RW_RW           (3 << 24)
  67 #define V7M_MPU_RASR_XN_ENABLE  (0 << 28)
  68 #define V7M_MPU_RASR_XN_DISABLE (1 << 28)
  69
  70 #endif /* !defined(__ASSEMBLY__) */
  71 #endif /* ARMV7M_H */