1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright (C) 2017, STMicroelectronics - All Rights Reserved
4 * Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics.
7 #ifndef _ASM_ARMV7_MPU_H
8 #define _ASM_ARMV7_MPU_H
17 #else /* CONFIG_CPU_V7R */
24 #endif /* CONFIG_CPU_V7R */
26 #define CACHEABLE BIT(C_SHIFT)
27 #define BUFFERABLE BIT(B_SHIFT)
28 #define SHAREABLE BIT(S_SHIFT)
29 #define REGION_SIZE_SHIFT 1
30 #define ENABLE_REGION BIT(0)
31 #define DISABLE_REGION 0
56 SHARED_WRITE_BUFFERED,
81 struct mpu_region_config {
83 enum region_number region_no;
90 void disable_mpu(void);
91 void enable_mpu(void);
92 int mpu_enabled(void);
93 void mpu_config(struct mpu_region_config *reg_config);
94 void setup_mpu_regions(struct mpu_region_config *rgns, u32 num_rgns);
96 static inline u32 get_attr_encoding(u32 mr_attr)
104 case SHARED_WRITE_BUFFERED:
107 case O_I_WT_NO_WR_ALLOC:
110 case O_I_WB_NO_WR_ALLOC:
111 attr = CACHEABLE | BUFFERABLE;
113 case O_I_NON_CACHEABLE:
114 attr = 1 << TEX_SHIFT;
116 case O_I_WB_RD_WR_ALLOC:
117 attr = (1 << TEX_SHIFT) | CACHEABLE | BUFFERABLE;
119 case DEVICE_NON_SHARED:
120 attr = (2 << TEX_SHIFT) | BUFFERABLE;
123 attr = 0; /* strongly ordered */
130 #endif /* _ASM_ARMV7_MPU_H */