3 * Texas Instruments, <www.ti.com>
4 * Aneesh V <aneesh@ti.com>
6 * SPDX-License-Identifier: GPL-2.0+
11 /* Cortex-A9 revisions */
12 #define MIDR_CORTEX_A9_R0P1 0x410FC091
13 #define MIDR_CORTEX_A9_R1P2 0x411FC092
14 #define MIDR_CORTEX_A9_R1P3 0x411FC093
15 #define MIDR_CORTEX_A9_R2P10 0x412FC09A
17 /* Cortex-A15 revisions */
18 #define MIDR_CORTEX_A15_R0P0 0x410FC0F0
19 #define MIDR_CORTEX_A15_R2P2 0x412FC0F2
21 /* Cortex-A7 revisions */
22 #define MIDR_CORTEX_A7_R0P0 0x410FC070
24 #define MIDR_PRIMARY_PART_MASK 0xFF0FFFF0
26 /* ID_PFR1 feature fields */
27 #define CPUID_ARM_SEC_SHIFT 4
28 #define CPUID_ARM_SEC_MASK (0xF << CPUID_ARM_SEC_SHIFT)
29 #define CPUID_ARM_VIRT_SHIFT 12
30 #define CPUID_ARM_VIRT_MASK (0xF << CPUID_ARM_VIRT_SHIFT)
31 #define CPUID_ARM_GENTIMER_SHIFT 16
32 #define CPUID_ARM_GENTIMER_MASK (0xF << CPUID_ARM_GENTIMER_SHIFT)
34 /* valid bits in CBAR register / PERIPHBASE value */
35 #define CBAR_MASK 0xFFFF8000
38 #define CCSIDR_LINE_SIZE_OFFSET 0
39 #define CCSIDR_LINE_SIZE_MASK 0x7
40 #define CCSIDR_ASSOCIATIVITY_OFFSET 3
41 #define CCSIDR_ASSOCIATIVITY_MASK (0x3FF << 3)
42 #define CCSIDR_NUM_SETS_OFFSET 13
43 #define CCSIDR_NUM_SETS_MASK (0x7FFF << 13)
46 * Values for InD field in CSSELR
47 * Selects the type of cache
49 #define ARMV7_CSSELR_IND_DATA_UNIFIED 0
50 #define ARMV7_CSSELR_IND_INSTRUCTION 1
52 /* Values for Ctype fields in CLIDR */
53 #define ARMV7_CLIDR_CTYPE_NO_CACHE 0
54 #define ARMV7_CLIDR_CTYPE_INSTRUCTION_ONLY 1
55 #define ARMV7_CLIDR_CTYPE_DATA_ONLY 2
56 #define ARMV7_CLIDR_CTYPE_INSTRUCTION_DATA 3
57 #define ARMV7_CLIDR_CTYPE_UNIFIED 4
60 #include <linux/types.h>
64 * CP15 Barrier instructions
65 * Please note that we have separate barrier instructions in ARMv7
66 * However, we use the CP15 based instructtions because we use
67 * -march=armv5 in U-Boot
69 #define CP15ISB asm volatile ("mcr p15, 0, %0, c7, c5, 4" : : "r" (0))
70 #define CP15DSB asm volatile ("mcr p15, 0, %0, c7, c10, 4" : : "r" (0))
71 #define CP15DMB asm volatile ("mcr p15, 0, %0, c7, c10, 5" : : "r" (0))
74 * Workaround for ARM errata # 798870
75 * Set L2ACTLR[7] to reissue any memory transaction in the L2 that has been
76 * stalled for 1024 cycles to verify that its hazard condition still exists.
78 static inline void v7_enable_l2_hazard_detect(void)
82 /* L2ACTLR[7]: Enable hazard detect timeout */
83 asm volatile ("mrc p15, 1, %0, c15, c0, 0\n\t" : "=r"(val));
85 asm volatile ("mcr p15, 1, %0, c15, c0, 0\n\t" : : "r"(val));
89 * Workaround for ARM errata # 799270
90 * Ensure that the L2 logic has been used within the previous 256 cycles
91 * before modifying the ACTLR.SMP bit. This is required during boot before
92 * MMU has been enabled, or during a specified reset or power down sequence.
94 static inline void v7_enable_smp(uint32_t address)
98 /* Read auxiliary control register */
99 asm volatile ("mrc p15, 0, %0, c1, c0, 1\n\t" : "=r"(val));
104 /* Dummy read to assure L2 access */
105 temp = readl(address);
109 /* Write auxiliary control register */
110 asm volatile ("mcr p15, 0, %0, c1, c0, 1\n\t" : : "r"(val));
116 void v7_en_l2_hazard_detect(void);
117 void v7_outer_cache_enable(void);
118 void v7_outer_cache_disable(void);
119 void v7_outer_cache_flush_all(void);
120 void v7_outer_cache_inval_all(void);
121 void v7_outer_cache_flush_range(u32 start, u32 end);
122 void v7_outer_cache_inval_range(u32 start, u32 end);
124 #if defined(CONFIG_ARMV7_NONSEC) || defined(CONFIG_ARMV7_VIRT)
126 int armv7_init_nonsec(void);
127 int armv7_update_dt(void *fdt);
128 bool armv7_boot_nonsec(void);
130 /* defined in assembly file */
131 unsigned int _nonsec_init(void);
132 void _do_nonsec_entry(void *target_pc, unsigned long r0,
133 unsigned long r1, unsigned long r2);
136 extern char __secure_start[];
137 extern char __secure_end[];
139 #endif /* CONFIG_ARMV7_NONSEC || CONFIG_ARMV7_VIRT */
141 #endif /* ! __ASSEMBLY__ */