1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * (C) Copyright 2014 - 2015 Xilinx, Inc.
4 * Michal Simek <michal.simek@xilinx.com>
7 #ifndef _ASM_ARCH_SYS_PROTO_H
8 #define _ASM_ARCH_SYS_PROTO_H
10 #define PAYLOAD_ARG_CNT 5
12 #define ZYNQMP_CSU_SILICON_VER_MASK 0xF
13 #define ZYNQMP_SIP_SVC_PM_SECURE_IMG_LOAD 0xC200002D
14 #define KEY_PTR_LEN 32
16 #define ZYNQMP_FPGA_BIT_AUTH_DDR 1
17 #define ZYNQMP_FPGA_BIT_AUTH_OCM 2
18 #define ZYNQMP_FPGA_BIT_ENC_USR_KEY 3
19 #define ZYNQMP_FPGA_BIT_ENC_DEV_KEY 4
20 #define ZYNQMP_FPGA_BIT_NS 5
22 #define ZYNQMP_FPGA_AUTH_DDR 1
24 #define ZYNQMP_SIP_SVC_GET_API_VERSION 0xC2000001
26 #define ZYNQMP_PM_VERSION_MAJOR 1
27 #define ZYNQMP_PM_VERSION_MINOR 0
28 #define ZYNQMP_PM_VERSION_MAJOR_SHIFT 16
29 #define ZYNQMP_PM_VERSION_MINOR_MASK 0xFFFF
31 #define ZYNQMP_PM_VERSION \
32 ((ZYNQMP_PM_VERSION_MAJOR << ZYNQMP_PM_VERSION_MAJOR_SHIFT) | \
33 ZYNQMP_PM_VERSION_MINOR)
53 int zynq_board_read_rom_ethaddr(unsigned char *ethaddr);
54 unsigned int zynqmp_get_silicon_version(void);
56 void handoff_setup(void);
58 void zynqmp_pmufw_version(void);
59 int zynqmp_mmio_write(const u32 address, const u32 mask, const u32 value);
60 int zynqmp_mmio_read(const u32 address, u32 *value);
61 int invoke_smc(u32 pm_api_id, u32 arg0, u32 arg1, u32 arg2, u32 arg3,
64 void initialize_tcm(bool mode);
65 void mem_map_fill(void);
66 int chip_id(unsigned char id);
68 #endif /* _ASM_ARCH_SYS_PROTO_H */