2 * UniPhier SG (SoC Glue) block registers
4 * Copyright (C) 2011-2014 Panasonic Corporation
6 * SPDX-License-Identifier: GPL-2.0+
10 #define ARCH_SG_REGS_H
13 #define SG_CTRL_BASE 0x5f800000
14 #define SG_DBG_BASE 0x5f900000
17 #define SG_REVISION (SG_CTRL_BASE | 0x0000)
18 #define SG_REVISION_TYPE_SHIFT 16
19 #define SG_REVISION_TYPE_MASK (0xff << SG_REVISION_TYPE_SHIFT)
20 #define SG_REVISION_MODEL_SHIFT 8
21 #define SG_REVISION_MODEL_MASK (0x3 << SG_REVISION_MODEL_SHIFT)
22 #define SG_REVISION_REV_SHIFT 0
23 #define SG_REVISION_REV_MASK (0x1f << SG_REVISION_REV_SHIFT)
25 /* Memory Configuration */
26 #define SG_MEMCONF (SG_CTRL_BASE | 0x0400)
28 #define SG_MEMCONF_CH0_SIZE_64MB ((0x0 << 10) | (0x01 << 0))
29 #define SG_MEMCONF_CH0_SIZE_128MB ((0x0 << 10) | (0x02 << 0))
30 #define SG_MEMCONF_CH0_SIZE_256MB ((0x0 << 10) | (0x03 << 0))
31 #define SG_MEMCONF_CH0_SIZE_512MB ((0x1 << 10) | (0x00 << 0))
32 #define SG_MEMCONF_CH0_SIZE_1024MB ((0x1 << 10) | (0x01 << 0))
33 #define SG_MEMCONF_CH0_NUM_1 (0x1 << 8)
34 #define SG_MEMCONF_CH0_NUM_2 (0x0 << 8)
36 #define SG_MEMCONF_CH1_SIZE_64MB ((0x0 << 11) | (0x01 << 2))
37 #define SG_MEMCONF_CH1_SIZE_128MB ((0x0 << 11) | (0x02 << 2))
38 #define SG_MEMCONF_CH1_SIZE_256MB ((0x0 << 11) | (0x03 << 2))
39 #define SG_MEMCONF_CH1_SIZE_512MB ((0x1 << 11) | (0x00 << 2))
40 #define SG_MEMCONF_CH1_SIZE_1024MB ((0x1 << 11) | (0x01 << 2))
41 #define SG_MEMCONF_CH1_NUM_1 (0x1 << 9)
42 #define SG_MEMCONF_CH1_NUM_2 (0x0 << 9)
44 #define SG_MEMCONF_SPARSEMEM (0x1 << 4)
47 #define SG_PINCTRL_BASE (SG_CTRL_BASE | 0x1000)
49 #if defined(CONFIG_MACH_PH1_PRO4)
50 # define SG_PINCTRL(n) (SG_PINCTRL_BASE + (n) * 8)
51 #elif defined(CONFIG_MACH_PH1_LD4) || defined(CONFIG_MACH_PH1_SLD8)
52 # define SG_PINCTRL(n) (SG_PINCTRL_BASE + (n) * 4)
55 #if defined(CONFIG_MACH_PH1_PRO4)
56 #define SG_PINSELBITS 4
57 #elif defined(CONFIG_MACH_PH1_LD4) || defined(CONFIG_MACH_PH1_SLD8)
58 #define SG_PINSELBITS 8
61 #define SG_PINSEL_ADDR(n) (SG_PINCTRL((n) * (SG_PINSELBITS) / 32))
62 #define SG_PINSEL_MASK(n) (~(((1 << (SG_PINSELBITS)) - 1) << \
63 ((n) * (SG_PINSELBITS) % 32)))
64 #define SG_PINSEL_MODE(n, mode) ((mode) << ((n) * (SG_PINSELBITS) % 32))
66 /* Only for PH1-Pro4 */
67 #define SG_LOADPINCTRL (SG_CTRL_BASE | 0x1700)
70 #define SG_IECTRL (SG_CTRL_BASE | 0x1d00)
73 #define SG_PINMON0 (SG_DBG_BASE | 0x0100)
75 #define SG_PINMON0_CLK_MODE_UPLLSRC_MASK (0x3 << 19)
76 #define SG_PINMON0_CLK_MODE_UPLLSRC_DEFAULT (0x0 << 19)
77 #define SG_PINMON0_CLK_MODE_UPLLSRC_VPLL27A (0x2 << 19)
78 #define SG_PINMON0_CLK_MODE_UPLLSRC_VPLL27B (0x3 << 19)
80 #define SG_PINMON0_CLK_MODE_AXOSEL_MASK (0x3 << 16)
81 #define SG_PINMON0_CLK_MODE_AXOSEL_24576KHZ (0x0 << 16)
82 #define SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ (0x1 << 16)
83 #define SG_PINMON0_CLK_MODE_AXOSEL_6144KHZ (0x2 << 16)
84 #define SG_PINMON0_CLK_MODE_AXOSEL_6250KHZ (0x3 << 16)
86 #define SG_PINMON0_CLK_MODE_AXOSEL_DEFAULT (0x0 << 16)
87 #define SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_U (0x1 << 16)
88 #define SG_PINMON0_CLK_MODE_AXOSEL_20480KHZ (0x2 << 16)
89 #define SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_A (0x3 << 16)
93 .macro set_pinsel, n, value, ra, rd
94 ldr \ra, =SG_PINSEL_ADDR(\n)
96 and \rd, \rd, #SG_PINSEL_MASK(\n)
97 orr \rd, \rd, #SG_PINSEL_MODE(\n, \value)
103 #include <linux/types.h>
106 static inline void sg_set_pinsel(int n, int value)
108 writel((readl(SG_PINSEL_ADDR(n)) & SG_PINSEL_MASK(n))
109 | SG_PINSEL_MODE(n, value), SG_PINSEL_ADDR(n));
112 static inline u32 sg_memconf_val_ch0(unsigned long size, int num)
114 int size_mb = (size >> 20) / num;
119 ret = SG_MEMCONF_CH0_SIZE_64MB;
122 ret = SG_MEMCONF_CH0_SIZE_128MB;
125 ret = SG_MEMCONF_CH0_SIZE_256MB;
128 ret = SG_MEMCONF_CH0_SIZE_512MB;
131 ret = SG_MEMCONF_CH0_SIZE_1024MB;
140 ret |= SG_MEMCONF_CH0_NUM_1;
143 ret |= SG_MEMCONF_CH0_NUM_2;
152 static inline u32 sg_memconf_val_ch1(unsigned long size, int num)
154 int size_mb = (size >> 20) / num;
159 ret = SG_MEMCONF_CH1_SIZE_64MB;
162 ret = SG_MEMCONF_CH1_SIZE_128MB;
165 ret = SG_MEMCONF_CH1_SIZE_256MB;
168 ret = SG_MEMCONF_CH1_SIZE_512MB;
171 ret = SG_MEMCONF_CH1_SIZE_1024MB;
180 ret |= SG_MEMCONF_CH1_NUM_1;
183 ret |= SG_MEMCONF_CH1_NUM_2;
191 #endif /* __ASSEMBLY__ */
193 #endif /* ARCH_SG_REGS_H */