2 * UniPhier SC (System Control) block registers
4 * Copyright (C) 2011-2014 Panasonic Corporation
6 * SPDX-License-Identifier: GPL-2.0+
10 #define ARCH_SC_REGS_H
12 #define SC_BASE_ADDR 0x61840000
14 #define SC_MPLLOSCCTL (SC_BASE_ADDR | 0x1184)
15 #define SC_MPLLOSCCTL_MPLLEN (0x1 << 0)
16 #define SC_MPLLOSCCTL_MPLLST (0x1 << 1)
18 #define SC_DPLLCTRL (SC_BASE_ADDR | 0x1200)
19 #define SC_DPLLCTRL_SSC_EN (0x1 << 31)
20 #define SC_DPLLCTRL_FOUTMODE_MASK (0xf << 16)
21 #define SC_DPLLCTRL_SSC_RATE (0x1 << 15)
23 #define SC_DPLLCTRL2 (SC_BASE_ADDR | 0x1204)
24 #define SC_DPLLCTRL2_NRSTDS (0x1 << 28)
26 #define SC_DPLLCTRL3 (SC_BASE_ADDR | 0x1208)
27 #define SC_DPLLCTRL3_LPFSEL_COEF2 (0x0 << 31)
28 #define SC_DPLLCTRL3_LPFSEL_COEF3 (0x1 << 31)
30 #define SC_UPLLCTRL (SC_BASE_ADDR | 0x1210)
32 #define SC_VPLL27ACTRL (SC_BASE_ADDR | 0x1270)
33 #define SC_VPLL27ACTRL2 (SC_BASE_ADDR | 0x1274)
34 #define SC_VPLL27ACTRL3 (SC_BASE_ADDR | 0x1278)
36 #define SC_VPLL27BCTRL (SC_BASE_ADDR | 0x1290)
37 #define SC_VPLL27BCTRL2 (SC_BASE_ADDR | 0x1294)
38 #define SC_VPLL27BCTRL3 (SC_BASE_ADDR | 0x1298)
40 #define SC_RSTCTRL (SC_BASE_ADDR | 0x2000)
41 #define SC_RSTCTRL_NRST_ETHER (0x1 << 12)
42 #define SC_RSTCTRL_NRST_UMC1 (0x1 << 5)
43 #define SC_RSTCTRL_NRST_UMC0 (0x1 << 4)
44 #define SC_RSTCTRL_NRST_NAND (0x1 << 2)
46 #define SC_RSTCTRL2 (SC_BASE_ADDR | 0x2004)
47 #define SC_RSTCTRL3 (SC_BASE_ADDR | 0x2008)
49 #define SC_CLKCTRL (SC_BASE_ADDR | 0x2104)
50 #define SC_CLKCTRL_CLK_ETHER (0x1 << 12)
51 #define SC_CLKCTRL_CLK_MIO (0x1 << 11)
52 #define SC_CLKCTRL_CLK_UMC (0x1 << 4)
53 #define SC_CLKCTRL_CLK_NAND (0x1 << 2)
54 #define SC_CLKCTRL_CLK_SBC (0x1 << 1)
55 #define SC_CLKCTRL_CLK_PERI (0x1 << 0)
57 /* System reset control register */
58 #define SC_IRQTIMSET (SC_BASE_ADDR | 0x3000)
59 #define SC_SLFRSTSEL (SC_BASE_ADDR | 0x3010)
60 #define SC_SLFRSTCTL (SC_BASE_ADDR | 0x3014)
62 #endif /* ARCH_SC_REGS_H */