2 * TNETV107X: Hardware information
4 * See file CREDITS for list of people who contributed to this
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
22 #ifndef __ASM_ARCH_HARDWARE_H
23 #define __ASM_ARCH_HARDWARE_H
27 #include <asm/sizes.h>
29 #define ASYNC_EMIF_NUM_CS 4
30 #define ASYNC_EMIF_MODE_NOR 0
31 #define ASYNC_EMIF_MODE_NAND 1
32 #define ASYNC_EMIF_MODE_ONENAND 2
33 #define ASYNC_EMIF_PRESERVE -1
35 struct async_emif_config {
37 unsigned select_strobe;
53 void init_async_emif(int num_cs, struct async_emif_config *config);
55 int wdt_start(unsigned long msecs);
61 /* Chip configuration unlock codes and registers */
62 #define TNETV107X_KICK0 (TNETV107X_CHIP_CONFIG_SYS_BASE+0x38)
63 #define TNETV107X_KICK1 (TNETV107X_CHIP_CONFIG_SYS_BASE+0x3c)
64 #define TNETV107X_PINMUX(n) (TNETV107X_CHIP_CONFIG_SYS_BASE+0x150+(n)*4)
65 #define TNETV107X_KICK0_MAGIC 0x83e70b13
66 #define TNETV107X_KICK1_MAGIC 0x95a4f1e0
68 /* Module base addresses */
69 #define TNETV107X_TPCC_BASE 0x01C00000
70 #define TNETV107X_TPTC0_BASE 0x01C10000
71 #define TNETV107X_TPTC1_BASE 0x01C10400
72 #define TNETV107X_INTC_BASE 0x03000000
73 #define TNETV107X_LCD_CONTROLLER_BASE 0x08030000
74 #define TNETV107X_INTD_BASE 0x08038000
75 #define TNETV107X_INTD_IPC_BASE 0x08038000
76 #define TNETV107X_INTD_FAST_BASE 0x08039000
77 #define TNETV107X_INTD_ASYNC_BASE 0x0803A000
78 #define TNETV107X_INTD_SLOW_BASE 0x0803B000
79 #define TNETV107X_PKA_BASE 0x08040000
80 #define TNETV107X_RNG_BASE 0x08044000
81 #define TNETV107X_TIMER0_BASE 0x08086500
82 #define TNETV107X_TIMER1_BASE 0x08086600
83 #define TNETV107X_WDT0_ARM_BASE 0x08086700
84 #define TNETV107X_WDT1_DSP_BASE 0x08086800
85 #define TNETV107X_CHIP_CONFIG_SYS_BASE 0x08087000
86 #define TNETV107X_GPIO_BASE 0x08088000
87 #define TNETV107X_UART1_BASE 0x08088400
88 #define TNETV107X_TOUCHSCREEN_BASE 0x08088500
89 #define TNETV107X_SDIO0_BASE 0x08088700
90 #define TNETV107X_SDIO1_BASE 0x08088800
91 #define TNETV107X_MDIO_BASE 0x08088900
92 #define TNETV107X_KEYPAD_BASE 0x08088A00
93 #define TNETV107X_SSP_BASE 0x08088C00
94 #define TNETV107X_CLOCK_CONTROL_BASE 0x0808A000
95 #define TNETV107X_PSC_BASE 0x0808B000
96 #define TNETV107X_TDM0_BASE 0x08100000
97 #define TNETV107X_TDM1_BASE 0x08100100
98 #define TNETV107X_MCDMA_BASE 0x08108000
99 #define TNETV107X_UART0_DMA_BASE 0x08108200
100 #define TNETV107X_USBSS_BASE 0x08120000
101 #define TNETV107X_VLYNQ_CONTROL_BASE 0x0810D000
102 #define TNETV107X_ASYNC_EMIF_CNTRL_BASE 0x08200000
103 #define TNETV107X_VLYNQ_MEM_MAP_BASE 0x0C000000
104 #define TNETV107X_IMCOP_BASE 0x01CC0000
105 #define TNETV107X_MBX_LITE_BASE 0x07000000
106 #define TNETV107X_ETHSS_BASE 0x0803C000
107 #define TNETV107X_CPSW_BASE 0x0803C000
108 #define TNETV107X_SPF_BASE 0x0803C800
109 #define TNETV107X_IOPU_ETHSS_BASE 0x0803D000
110 #define TNETV107X_VTP_CNTRL_0 0x0803D800
111 #define TNETV107X_VTP_CNTRL_1 0x0803D900
112 #define TNETV107X_UART2_DMA_BASE 0x08108400
113 #define TNETV107X_INTERNAL_MEMORY 0x20000000
114 #define TNETV107X_ASYNC_EMIF_DATA_CE0_BASE 0x30000000
115 #define TNETV107X_ASYNC_EMIF_DATA_CE1_BASE 0x40000000
116 #define TNETV107X_ASYNC_EMIF_DATA_CE2_BASE 0x44000000
117 #define TNETV107X_ASYNC_EMIF_DATA_CE3_BASE 0x48000000
118 #define TNETV107X_DDR_EMIF_DATA_BASE 0x80000000
119 #define TNETV107X_DDR_EMIF_CONTROL_BASE 0x90000000
121 /* LPSC module definitions */
122 #define TNETV107X_LPSC_ARM 0
123 #define TNETV107X_LPSC_GEM 1
124 #define TNETV107X_LPSC_DDR2_PHY 2
125 #define TNETV107X_LPSC_TPCC 3
126 #define TNETV107X_LPSC_TPTC0 4
127 #define TNETV107X_LPSC_TPTC1 5
128 #define TNETV107X_LPSC_RAM 6
129 #define TNETV107X_LPSC_MBX_LITE 7
130 #define TNETV107X_LPSC_LCD 8
131 #define TNETV107X_LPSC_ETHSS 9
132 #define TNETV107X_LPSC_AEMIF 10
133 #define TNETV107X_LPSC_CHIP_CFG 11
134 #define TNETV107X_LPSC_TSC 12
135 #define TNETV107X_LPSC_ROM 13
136 #define TNETV107X_LPSC_UART2 14
137 #define TNETV107X_LPSC_PKTSEC 15
138 #define TNETV107X_LPSC_SECCTL 16
139 #define TNETV107X_LPSC_KEYMGR 17
140 #define TNETV107X_LPSC_KEYPAD 18
141 #define TNETV107X_LPSC_GPIO 19
142 #define TNETV107X_LPSC_MDIO 20
143 #define TNETV107X_LPSC_SDIO0 21
144 #define TNETV107X_LPSC_UART0 22
145 #define TNETV107X_LPSC_UART1 23
146 #define TNETV107X_LPSC_TIMER0 24
147 #define TNETV107X_LPSC_TIMER1 25
148 #define TNETV107X_LPSC_WDT_ARM 26
149 #define TNETV107X_LPSC_WDT_DSP 27
150 #define TNETV107X_LPSC_SSP 28
151 #define TNETV107X_LPSC_TDM0 29
152 #define TNETV107X_LPSC_VLYNQ 30
153 #define TNETV107X_LPSC_MCDMA 31
154 #define TNETV107X_LPSC_USB0 32
155 #define TNETV107X_LPSC_TDM1 33
156 #define TNETV107X_LPSC_DEBUGSS 34
157 #define TNETV107X_LPSC_ETHSS_RGMII 35
158 #define TNETV107X_LPSC_SYSTEM 36
159 #define TNETV107X_LPSC_IMCOP 37
160 #define TNETV107X_LPSC_SPARE 38
161 #define TNETV107X_LPSC_SDIO1 39
162 #define TNETV107X_LPSC_USB1 40
163 #define TNETV107X_LPSC_USBSS 41
164 #define TNETV107X_LPSC_DDR2_EMIF1_VRST 42
165 #define TNETV107X_LPSC_DDR2_EMIF2_VCTL_RST 43
166 #define TNETV107X_LPSC_MAX 44
168 /* Interrupt controller */
169 #define INTC_GLB_EN (TNETV107X_INTC_BASE + 0x10)
170 #define INTC_HINT_EN (TNETV107X_INTC_BASE + 0x1500)
171 #define INTC_EN_CLR0 (TNETV107X_INTC_BASE + 0x380)
173 #endif /* __ASM_ARCH_HARDWARE_H */