1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved.
6 /* Tegra30 clock PLL tables */
8 #ifndef _TEGRA30_CLOCK_TABLES_H_
9 #define _TEGRA30_CLOCK_TABLES_H_
11 /* The PLLs supported by the hardware */
14 CLOCK_ID_CGENERAL = CLOCK_ID_FIRST,
21 /* now the simple ones */
22 CLOCK_ID_FIRST_SIMPLE,
23 CLOCK_ID_XCPU = CLOCK_ID_FIRST_SIMPLE,
27 /* These are the base clocks (inputs to the Tegra SOC) */
32 CLOCK_ID_COUNT, /* number of PLLs */
33 CLOCK_ID_DISPLAY2, /* Tegra3, placeholder */
37 /* The clocks supported by the hardware */
42 PERIPH_ID_CPU = PERIPH_ID_FIRST,
81 /* Middle word: 63:32 */
112 PERIPH_ID_RESERVED56,
121 /* Upper word 95:64 */
136 PERIPH_ID_RESERVED76,
137 PERIPH_ID_RESERVED77,
138 PERIPH_ID_RESERVED78,
145 PERIPH_ID_RESERVED83,
153 PERIPH_ID_RESERVED89,
155 PERIPH_ID_RESERVED91,
157 PERIPH_ID_RESERVED93,
158 PERIPH_ID_RESERVED94,
159 PERIPH_ID_RESERVED95,
163 PERIPH_ID_CPUG = PERIPH_ID_VW_FIRST,
180 PERIPH_ID_HDA2CODEC2X,
184 PERIPH_ID_EX_RESERVED17,
185 PERIPH_ID_EX_RESERVED18,
186 PERIPH_ID_EX_RESERVED19,
187 PERIPH_ID_EX_RESERVED20,
188 PERIPH_ID_EX_RESERVED21,
189 PERIPH_ID_EX_RESERVED22,
193 PERIPH_ID_EX_RESERVED24,
194 PERIPH_ID_EX_RESERVED25,
195 PERIPH_ID_EX_RESERVED26,
196 PERIPH_ID_EX_RESERVED27,
199 PERIPH_ID_EX_RESERVED30,
200 PERIPH_ID_EX_RESERVED31,
203 PERIPH_ID_HDA2HDMICODEC,
205 PERIPH_ID_RESERVED0_PCIERX0,
206 PERIPH_ID_RESERVED1_PCIERX1,
207 PERIPH_ID_RESERVED2_PCIERX2,
208 PERIPH_ID_RESERVED3_PCIERX3,
209 PERIPH_ID_RESERVED4_PCIERX4,
210 PERIPH_ID_RESERVED5_PCIERX5,
214 PERIPH_ID_RESERVED6_PCIE2,
215 PERIPH_ID_RESERVED7_EMC,
216 PERIPH_ID_RESERVED8_HDMI,
217 PERIPH_ID_RESERVED9_SATA,
218 PERIPH_ID_RESERVED10_MIPI,
219 PERIPH_ID_EX_RESERVED46,
220 PERIPH_ID_EX_RESERVED47,
234 * Clock peripheral IDs which sadly don't match up with PERIPH_ID. we want
235 * callers to use the PERIPH_ID for all access to peripheral clocks to avoid
236 * confusion bewteen PERIPH_ID_... and PERIPHC_...
238 * We don't call this CLOCK_PERIPH_ID or PERIPH_CLOCK_ID as it would just be
241 enum periphc_internal_id {
314 PERIPHC_G3D2 = PERIPHC_VW_FIRST,
357 /* Converts a clock number to a clock register: 0=L, 1=H, 2=U, 0=V, 1=W */
358 #define PERIPH_REG(id) \
359 (id < PERIPH_ID_VW_FIRST) ? \
360 ((id) >> 5) : ((id - PERIPH_ID_VW_FIRST) >> 5)
362 /* Mask value for a clock (within PERIPH_REG(id)) */
363 #define PERIPH_MASK(id) (1 << ((id) & 0x1f))
365 /* return 1 if a PLL ID is in range */
366 #define clock_id_is_pll(id) ((id) >= CLOCK_ID_FIRST && (id) < CLOCK_ID_COUNT)
368 /* return 1 if a peripheral ID is in range */
369 #define clock_periph_id_isvalid(id) ((id) >= PERIPH_ID_FIRST && \
370 (id) < PERIPH_ID_COUNT)
372 #endif /* _TEGRA30_CLOCK_TABLES_H_ */