arch/arm/include/asm/arch-tegra20/sdram_param.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  *  (C) Copyright 2010, 2011
   4  *  NVIDIA Corporation <www.nvidia.com>
   5  */
   6
   7 #ifndef _SDRAM_PARAM_H_
   8 #define _SDRAM_PARAM_H_
   9
  10 /*
  11  * Defines the number of 32-bit words provided in each set of SDRAM parameters
  12  * for arbitration configuration data.
  13  */
  14 #define BCT_SDRAM_ARB_CONFIG_WORDS 27
  15
  16 enum memory_type {
  17         MEMORY_TYPE_NONE = 0,
  18         MEMORY_TYPE_DDR,
  19         MEMORY_TYPE_LPDDR,
  20         MEMORY_TYPE_DDR2,
  21         MEMORY_TYPE_LPDDR2,
  22         MEMORY_TYPE_NUM,
  23         MEMORY_TYPE_FORCE32 = 0x7FFFFFFF
  24 };
  25
  26 /* Defines the SDRAM parameter structure */
  27 struct sdram_params {
  28         enum memory_type memory_type;
  29         u32 pllm_charge_pump_setup_control;
  30         u32 pllm_loop_filter_setup_control;
  31         u32 pllm_input_divider;
  32         u32 pllm_feedback_divider;
  33         u32 pllm_post_divider;
  34         u32 pllm_stable_time;
  35         u32 emc_clock_divider;
  36         u32 emc_auto_cal_interval;
  37         u32 emc_auto_cal_config;
  38         u32 emc_auto_cal_wait;
  39         u32 emc_pin_program_wait;
  40         u32 emc_rc;
  41         u32 emc_rfc;
  42         u32 emc_ras;
  43         u32 emc_rp;
  44         u32 emc_r2w;
  45         u32 emc_w2r;
  46         u32 emc_r2p;
  47         u32 emc_w2p;
  48         u32 emc_rd_rcd;
  49         u32 emc_wr_rcd;
  50         u32 emc_rrd;
  51         u32 emc_rext;
  52         u32 emc_wdv;
  53         u32 emc_quse;
  54         u32 emc_qrst;
  55         u32 emc_qsafe;
  56         u32 emc_rdv;
  57         u32 emc_refresh;
  58         u32 emc_burst_refresh_num;
  59         u32 emc_pdex2wr;
  60         u32 emc_pdex2rd;
  61         u32 emc_pchg2pden;
  62         u32 emc_act2pden;
  63         u32 emc_ar2pden;
  64         u32 emc_rw2pden;
  65         u32 emc_txsr;
  66         u32 emc_tcke;
  67         u32 emc_tfaw;
  68         u32 emc_trpab;
  69         u32 emc_tclkstable;
  70         u32 emc_tclkstop;
  71         u32 emc_trefbw;
  72         u32 emc_quseextra;
  73         u32 emc_fbioc_fg1;
  74         u32 emc_fbio_dqsib_dly;
  75         u32 emc_fbio_dqsib_dly_msb;
  76         u32 emc_fbio_quse_dly;
  77         u32 emc_fbio_quse_dly_msb;
  78         u32 emc_fbio_cfg5;
  79         u32 emc_fbio_cfg6;
  80         u32 emc_fbio_spare;
  81         u32 emc_mrs;
  82         u32 emc_emrs;
  83         u32 emc_mrw1;
  84         u32 emc_mrw2;
  85         u32 emc_mrw3;
  86         u32 emc_mrw_reset_command;
  87         u32 emc_mrw_reset_init_wait;
  88         u32 emc_adr_cfg;
  89         u32 emc_adr_cfg1;
  90         u32 emc_emem_cfg;
  91         u32 emc_low_latency_config;
  92         u32 emc_cfg;
  93         u32 emc_cfg2;
  94         u32 emc_dbg;
  95         u32 ahb_arbitration_xbar_ctrl;
  96         u32 emc_cfg_dig_dll;
  97         u32 emc_dll_xform_dqs;
  98         u32 emc_dll_xform_quse;
  99         u32 warm_boot_wait;
 100         u32 emc_ctt_term_ctrl;
 101         u32 emc_odt_write;
 102         u32 emc_odt_read;
 103         u32 emc_zcal_ref_cnt;
 104         u32 emc_zcal_wait_cnt;
 105         u32 emc_zcal_mrw_cmd;
 106         u32 emc_mrs_reset_dll;
 107         u32 emc_mrw_zq_init_dev0;
 108         u32 emc_mrw_zq_init_dev1;
 109         u32 emc_mrw_zq_init_wait;
 110         u32 emc_mrs_reset_dll_wait;
 111         u32 emc_emrs_emr2;
 112         u32 emc_emrs_emr3;
 113         u32 emc_emrs_ddr2_dll_enable;
 114         u32 emc_mrs_ddr2_dll_reset;
 115         u32 emc_emrs_ddr2_ocd_calib;
 116         u32 emc_edr2_wait;
 117         u32 emc_cfg_clktrim0;
 118         u32 emc_cfg_clktrim1;
 119         u32 emc_cfg_clktrim2;
 120         u32 pmc_ddr_pwr;
 121         u32 apb_misc_gp_xm2cfga_padctrl;
 122         u32 apb_misc_gp_xm2cfgc_padctrl;
 123         u32 apb_misc_gp_xm2cfgc_padctrl2;
 124         u32 apb_misc_gp_xm2cfgd_padctrl;
 125         u32 apb_misc_gp_xm2cfgd_padctrl2;
 126         u32 apb_misc_gp_xm2clkcfg_padctrl;
 127         u32 apb_misc_gp_xm2comp_padctrl;
 128         u32 apb_misc_gp_xm2vttgen_padctrl;
 129         u32 arbitration_config[BCT_SDRAM_ARB_CONFIG_WORDS];
 130 };
 131 #endif