arch/arm/include/asm/arch-tegra20/mc.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  *  (C) Copyright 2014
   4  *  NVIDIA Corporation <www.nvidia.com>
   5  */
   6
   7 #ifndef _TEGRA20_MC_H_
   8 #define _TEGRA20_MC_H_
   9
  10 /**
  11  * Defines the memory controller registers we need/care about
  12  */
  13 struct mc_ctlr {
  14         u32 reserved0[3];                       /* offset 0x00 - 0x08 */
  15         u32 mc_emem_cfg;                        /* offset 0x0C */
  16         u32 mc_emem_adr_cfg;                    /* offset 0x10 */
  17         u32 mc_emem_arb_cfg0;                   /* offset 0x14 */
  18         u32 mc_emem_arb_cfg1;                   /* offset 0x18 */
  19         u32 mc_emem_arb_cfg2;                   /* offset 0x1C */
  20         u32 reserved1;                          /* offset 0x20 */
  21         u32 mc_gart_cfg;                        /* offset 0x24 */
  22         u32 mc_gart_entry_addr;                 /* offset 0x28 */
  23         u32 mc_gart_entry_data;                 /* offset 0x2C */
  24         u32 mc_gart_error_req;                  /* offset 0x30 */
  25         u32 mc_gart_error_addr;                 /* offset 0x34 */
  26         u32 reserved2;                          /* offset 0x38 */
  27         u32 mc_timeout_ctrl;                    /* offset 0x3C */
  28         u32 reserved3[6];                       /* offset 0x40 - 0x54 */
  29         u32 mc_decerr_emem_others_status;       /* offset 0x58 */
  30         u32 mc_decerr_emem_others_adr;          /* offset 0x5C */
  31         u32 reserved4[40];                      /* offset 0x60 - 0xFC */
  32         u32 reserved5[93];                      /* offset 0x100 - 0x270 */
  33 };
  34
  35 #endif  /* _TEGRA20_MC_H_ */